參數(shù)資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 64/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
18
Figure 4. Top Level Overview, RX Path Logic, Single Channel
In either the SONET or cell mode, data from the DEMUX is then passed through a framer which word aligns and
frames the data. Data are then processed based on cell mode or SONET mode selection.
In the SONET mode, the descrambled data are sent to an alignment FIFO that performs lane-to-lane deskew and
optionally aligns data within a multi-channel alignment group. In addition, supervisory features such as BIP error
check, OOF check, RDI monitoring and AIS-L insertion during OOF are also implemented. All the supervisory fea-
tures are controlled through programmable register bits.
In the cell mode, the framed data are then descrambled and passed into a cell extractor which extracts cells from
the payload portion of the SONET frame. The cells are passed through a FIFO that performs lane-to-lane deskew
and a clock domain transfer from 77.76 MHz to 155.52 MHz. A key feature in cell mode is the ability to use idle cell
insertion and deletion for automatic rate matching between the clock domains. The cells are then passed to the
IPC2 block (or, in the ORSO82G5, to the IPC8 block) which perform cell destriping before sending the cells to the
FPGA logic across the Core/FPGA interface.
SERDES Transmit and Receive PLLs
The high-speed transmit and receive serial data can operate at 0.6 to 2.7 Gbps depending on the state of the con-
trol bits from the system bus. Table 2 shows the relationship between the data rates, the reference clock, and the
internal transmit TCK78x clocks.
Legend:
RCK78x
x = A for Block A, B for Block B
RWCKxx
xx = [AC, AD, BC, BD] for ORSO42G5
xx = [AA...BD] for ORSO82G5
IPCj_DOUT
j = [A2, B2] for ORSO42G5
j = [A1, A2, B1, B2, 8] for ORSO82G5
FP = Frame Pulse
Line Key:
SERDES-Only Mode
SONET Mode
Cell Mode
Cell/SONET or All Modes
1:8
Demux
FPGA
Logic
Data to
FPGA
Embedded Core
8:32
Demux
Channel
Alignment
FIFO
SONET
Framer/
Descrambler
Cell Extractor,
RXFIFO
IPC2 or IPC8
SONET Processing
Cell Processing
600Mb/s
-2.7Gbps
SERDES
8
LDOUT
RBC
REFCLK (155.52MHz)
nominal
SPE
Generator
SPE
32
FP
IPCj_DOUT
SYSCLK156x[1,2]
32
FP
From Other
Links in Block
77.76 MHz
RCK78x
RW CKxx
RSYSCLKx[1,2]
DOUTxx[31: 0]
DOUTxx_FP
Logic Common to Block
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ORSO42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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