參數(shù)資料
型號： ORSO42G5-2BM484I
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 25/153頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 4CH 484-BGA
產品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 60
系列： *
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
120
Package Information
Package Pinouts
Table 50 provides the number of user-programmable I/Os available for each available package.
Table 50. I/O Summary
Table 51 provides the package pin and pin function for the ORSO42G5 and ORSO82G5 FPSC and packages. The
bond pad name is identied in the PIO nomenclature used in the ispLEVER System software design editor. The
Bank column provides information as to which output voltage level bank the given pin is in. The Group column pro-
vides information as to the group of pins the given pin is in. This is used to show which VREF pin is used to provide
the reference voltage for single-ended limited-swing I/Os. If none of these buffer types (such as SSTL, GTL, HSTL)
are used in a given group, then the VREF pin is available as an I/O pin.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specic die, it is indicated as a note in the device column for
the FPGA. The tables provide no information on unused pads.
The differential pairs within each bank are physically arranged so that the ball locations for the pair are adjacent in
either the horizontal, vertical or diagonal directions.
VREF pins, shown in the Pin Description columns in Table 51 are associated to the bank and group (e.g.,
VREF_TL_01 is the VREF for group one of the Top Left (TL) bank.
Device
ORSO42G5
ORSO82G5
User programmable I/O
204
372
Available programmable differential pair pins
166
330
FPGA conguration pins
7
FPGA dedicated function pins
2
Core function pins
32
71
VDD15
49
63
VDD33
8
10
VDDIO
34
32
VSS
112
91
VDDGB
2
VDDIB
4
8
VDDOB
8
12
VDD_ANA
22
8
Core LV_REF pins
1
No connect
0
2
Total package pins
484
680
Table 51. ORSO42G5 484-pin PBGAM Pinout
484-PBGAM
VDDIO Bank
VREF Group
I/O
Pin Description
Additional Function
484-PBGAM
E4
-
O
PRD_DATA
RD_DATA/TDO
-
C20
-
VDD15
-
D3
-
I
PRESET_N
RESET_N
-
F5
-
I
PRD_CFG_N
RD_CFG_N
-
F4
-
I
PPRGRM_N
PRGRM_N
-
C2
0 (TL)
7
IO
PL2D
PLL_CK0C/HPPLL
L1C
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相關代理商/技術參數(shù)
參數(shù)描述
ORSO42G5-2BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-2BMN484I 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BM484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-3BMN484C 功能描述:FPGA - 現(xiàn)場可編程門陣列 10368 LUT 204 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORSO42G5-EV 功能描述:可編程邏輯 IC 開發(fā)工具 Eval Brd ORSO42G5 RoHS:否 制造商:Altera Corporation 產品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
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