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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 12/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
12
12/15/98 5:14 PM 24377002.doc
Table 1. Core Frequency to System Bus Multiplier Configuration
Multiplication of
Processor Core
Frequency to System
Bus Frequency
Product
Supported on
LINT[1]
LINT[0]
A20M#
IGNNE#
1/2
Reset only
L
L
L
L
1/3
Not Supported
L
L
L
H
1/4
400, 450 MHz
L
L
H
L
1/5
Not Supported
L
L
H
H
2/5
Not Supported
L
H
L
L
2/7
Not Supported
L
H
L
H
2/9
450 MHz
L
H
H
L
2/11
Not Supported
L
H
H
H
1/6
Not Supported
H
L
L
L
1/7
Not Supported
H
L
L
H
1/8
Not Supported
H
L
H
L
Reserved
Not Supported
H
L
H
H
2/13
Not Supported
H
H
L
L
2/15
Not Supported
H
H
L
H
2/3
Not Supported
H
H
H
L
1/2
Reset Only
H
H
H
H
See Figure 1 for the timing relationship between the
system bus multiplier signals, RESET#, and normal
processor operation. Using CRESET# (CMOS
Reset) and the timing shown in Figure 1, the circuit in
Figure 2 can be used to share these configuration
signals. The component used as the multiplexer must
not have outputs that drive higher than 2.5 V in order
to meet the processor’s 2.5 V tolerant buffer
specifications. The multiplexer output current should
be limited to 200 mA maximum, in case the V
CCCORE
supply to the processor ever fails.
As shown in Figure 2, the pull-up resistors between
the multiplexer and the processor (1k
) force a
“safe” ratio into the processor in the event that the
processor powers up before the multiplexer and/or
core logic. This prevents the processor from ever
seeing a ratio higher than the final ratio.
If the multiplexer were powered by V
CC2.5
, a pull-
down resistor could be used on CRESET# instead of
the four pull-up resistors between the multiplexer and
the Pentium II Xeon processors. In this case, the
multiplexer must be designed such that the
compatibility inputs are truly ignored, as their state is
unknown.
In any case, the compatibility inputs to the multiplexer
must meet the input specifications of the multiplexer.
This may require a level translation before the
multiplexer inputs unless the inputs and the signals
driving them are already compatible.
For FRC mode operation, these inputs to the
processor must be synchronized using BCLK to
meet setup and hold times to the processors. This
may require the use of high-speed programmable
logic.
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