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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 38/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
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12/15/98 5:14 PM 24377002.doc
Table 21. 2.5 V Tolerant Signal Overshoot/Undershoot Guidelines at the Processor Core
Guideline
Transition
Signal Must Maintain
Unit
Figure
Overshoot
0
→
1
< 3.2
V
15
Undershoot
1
→
0
> -0.3
V
15
Table 22. Signal Ringback Specifications for 2.5 V Tolerant Signal Simulation at the Processor Core
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0
→
1
1.7
V
15
Non-AGTL+ Signals
1
→
0
0.7
V
15
3.3.2.
2.5 V TOLERANT BUFFER RINGBACK
SPECIFICATION
The ringback specification is the voltage at a
receiving pin that a signal rings back to after
achieving its maximum absolute value (See
Figure 15 for an illustration of ringback.) Excessive
ringback can cause false signal detection or extend
the propagation delay. Violations of the signal
ringback specification are not allowed for 2.5 V
tolerant signals.
Table 22 shows signal ringback specifications for the
2.5 V tolerant signals to be used for simulations at
the processor core.
3.3.3.
2.5 V TOLERANT BUFFER SETTLING
LIMIT GUIDELINE
Settling limit defines the maximum amount of ringing
at the receiving pin that a signal must reach before its
next transition. The amount allowed is 10% of the
total signal swing (V
HI
– V
LO
) above and below its
final value. A signal should be within the settling limits
of its final value, when either in its high state or low
state, before it transitions again.
Violation of the settling limit guideline is acceptable if
simulations of 5 to 10 successive transitions do not
show the amplitude of the ringing increasing in the
subsequent transitions.
4.0.
PROCESSOR FEATURES
4.1.
Functional Redundancy
Checking Mode
Two Pentium II Xeon processor agents may be
configured as an FRC (functional redundancy
checking) pair. In this configuration, one processor
acts as the master and the other acts as a checker,
and the pair operates as a single processor. If the
checker agent detects a mismatch between its
internally
sampled
outputs
processor’s outputs, the checker asserts FRCERR.
FRCERR observation can be enabled at the master
processor with software. The master enters machine
check on an FRCERR provided that Machine Check
Execution is enabled.
and
the
master
Processors configured as FRC pairs must be of the
same frequency, stepping, and cache size.
ITP operation is not supported in FRC mode.
Systems configured to implement FRC mode must
write all of the processors’ internal MSRs to
deterministic values before performing either a read
or read-modify-write operation using these registers.
The following is a list of MSRs that are not initialized
by the processors' reset sequences.
1.
All fixed and variable MTRRs,
2.
All Machine Check Architecture (MCA) status
registers,
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