
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/15/98 5:14 PM 24377002.doc
2.4.1.
MIXING PROCESSORS OF
DIFFERENT FREQUENCIES AND
CACHE SIZES
Mixing components of different internal clock
frequencies is not supported and has not been
validated by Intel. Operating system support for MP
with mixed frequency components should also be
considered.
Also, Intel does not support or validate operation of
processors with different cache sizes. Intel only
supports and validates multiprocessor configurations
where all processors operate with the same system
bus and core frequencies and have the same L1 and
L2 cache sizes.
2.5.
Voltage Identification
The Pentium II Xeon processor contains five voltage
identification pins for core voltage selection and five
voltage identification pins for L2 cache voltage
selection. These pins may be used to support
automatic selection of both power supply voltages.
VID_CORE[4:0] controls the voltage supply to the
processor core and VID_L2[4:0] controls the voltage
supply to the L2 cache. Both use the same encoding
as shown in Table 2. They are not driven signals, but
are either an open circuit or a short circuit to V
SS
.
The combination of opens and shorts defines the
voltage required by the processor core and L2
cache. The VID pins support variations in processor
core voltage specifications and in L2 cache
implementations among processors in the Pentium II
Xeon
processor
family.
recommended range of values to support for both the
processor core and the L2 cache. A ‘1’ in this table
refers to an open pin and ‘0’ refers to a short to
ground. The definition provided below is a superset
of the definition previously defined for the Pentium
Pro processor (VID4 was not used by the Pentium
Pro processor) and is common to both the Pentium II
and Pentium II Xeon processors.
The power supply
must supply the voltage that is requested orit
must disable itself.
Table 2
shows
the
To ensure the system is ready for all Pentium II Xeon
processors, a system should support those voltages
indicated with a bold
x
in Table 2. Supporting a
smaller range will risk the ability of the system to
migrate to possible higher performance processors in
the future. Support for a wider range provides more
flexibility and is acceptable.