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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 82/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
82
12/15/98 5:14 PM 24377002.doc
Table 43. Debug Port Pinout Description and Requirements
1
(Continued)
Name
Pin
Description
Specification Requirement
Notes
bus agents if routed properly.
PREQ3#
28
PREQ3# signal from ITP to
P3.
Add 150 to 330
pull-up
resistor (to V
CC2.5
)
PRDY3#
30
PRDY3# signal from ITP to
P3.
Terminate
2
signal properly at
the debug port
Debug port must be at the
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on the ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents if routed properly.
BCLK
29
Bus clock from the MP
cluster.
Use a separate driver to drive
signal to the debug port
Must be connected to support
future steppings of the
Pentium II Xeon processor.
A separate driver should be
used to avoid loading issues
associated with having the
ITP either installed or not
installed.
GND
2, 4, 6, 13,
15, 17, 19,
21, 23, 25,
27
Signal ground.
Connect all pins to signal
ground
NOTES:
1.
Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to the value
specified.
Termination should include series (~240
) and GTL+ termination (connected to 1.5 V) resistors. See Figure 35.
Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to
assist in debugging the system: one partition with only the processor(s) for system debug (i.e., used with the ITP) and
another with all other components for manufacturing or system test.
2.
3.
8.1.4.
DEBUG PORT SIGNAL NOTES
In general, all open drain AGTL+ outputs from the
system must be retained at a proper logic level,
whether or not the debug port is installed. RESET#
from the processor system should be terminated at
the debug port, as shown in Figure 35. R
t
should be
a 150
on RESET#.
PRDYn# should have a similar layout, however R
t
should be 50
to match board impedance rather
than the normal 150
since there are only 2 loads on
this signal.
Debug
Port
Load
Load
Rt
Rs
1.5V
RESET#
Source
Rs
Short Trace
3770-35
Figure 35. AGTL+ Signal Termination
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