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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 3/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
3
12/16/98 1:23 PM 24377003.doc
CONTENTS
PAGE
PAGE
1.0. INTRODUCTION...............................................8
1.1.Terminology....................................................8
1.1.1. S.E.C. Cartridge Terminology.................8
1.2. References.....................................................9
2.0. ELECTRICAL SPECIFICATIONS....................9
2.1. The Pentium II Xeon Processor System
Bus and VREF...............................................9
2.2. Power and Ground Pins...............................10
2.3. Decoupling Guidelines.................................10
2.3.1. PENTIUM II XEON PROCESSOR
VCCCORE............................................11
2.3.2. LEVEL 2 CACHE DECOUPLING ........11
2.3.3. SYSTEM BUS AGTL+
DECOUPLING......................................11
2.4. System Bus Clock and Processor
Clocking.......................................................11
2.4.1. MIXING PROCESSORS OF
DIFFERENT FREQUENCIES AND
CACHE SIZES......................................14
2.5.Voltage Identification ....................................14
2.6.System Bus Unused Pins and Test Pins .....16
2.7. System Bus Signal Groups..........................16
2.7.1. ASYNCHRONOUS VS.
SYNCHRONOUS FOR SYSTEM BUS
SIGNALS..............................................18
2.8. Test Access Port (TAP) Connection............18
2.9. Maximum Ratings........................................18
2.10. Processor DC Specifications..................19
2.11. AGTL+ System Bus Specifications.........23
2.12. System Bus AC Specifications ...............24
3.0. SIGNAL QUALITY..........................................33
3.1. System Bus Clock Signal Quality
Specifications...............................................34
3.2. AGTL+ Signal Quality Specifications...........35
3.2.1. AGTL+ RINGBACK TOLERANCE
SPECIFICATIONS ...............................35
3.2.2. AGTL+ OVERSHOOT/UNDERSHOOT
GUIDELINES........................................36
3.3. Non-AGTL+ Signal Quality Specifications...37
3.3.1. 2.5 V TOLERANT BUFFER
OVERSHOOT/UNDERSHOOT
GUIDELINES........................................37
3.3.2. 2.5 V TOLERANT BUFFER RINGBACK
SPECIFICATION..................................38
3.3.3. 2.5 V TOLERANT BUFFER SETTLING
LIMIT GUIDELINE................................38
4.0. PROCESSOR FEATURES.............................38
4.1. Functional Redundancy Checking Mode.....38
4.2. Low Power States and Clock Control..........39
4.2.1. NORMAL STATE—STATE 1...............39
4.2.2. AUTO HALT POWER DOWN
STATE—STATE 2................................39
4.2.3. STOP-GRANT STATE—STATE 3.......40
4.2.4. HALT/GRANT SNOOP STATE—
STATE 4 ...............................................40
4.2.5. SLEEP STATE—STATE 5...................41
4.2.6. CLOCK CONTROL ..............................41
4.3. System Management Bus (SMBus)
Interface.......................................................41
4.3.1. PROCESSOR INFORMATION ROM..42
4.3.2. SCRATCH EEPROM ...........................45
4.3.3. PROCESSOR INFORMATION ROM
AND SCRATCH EEPROM
SUPPORTED SMBUS
TRANSACTIONS .................................45
4.3.4. THERMAL SENSOR............................46
4.3.5. THERMAL SENSOR SUPPORTED
SMBUS TRANSACTIONS ...................47
4.3.6. THERMAL SENSORS REGISTERS ...49
4.3.6.1. Thermal Reference Registers........49
4.3.6.2. Thermal Limit Registers.................49
4.3.6.3. Status Register ..............................49
4.3.6.4. Configuration Register...................49
4.3.6.5. Conversion Rate Register..............50
4.3.7. SMBUS DEVICE ADDRESSING.........50
5.0. THERMAL SPECIFICATIONS AND DESIGN
CONSIDERATIONS........................................52
5.1. Thermal Specifications.................................52
5.1.1. POWER DISSIPATION........................53
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