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| 型號(hào)： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 91/97頁 |
| 文件大小： | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
91
12/15/98 5:14 PM 24377002.doc
9.1.29.
LOCK# (I/O)
The LOCK# signal indicates to the system that a
transaction must occur atomically. This signal must
connect the appropriate pins of all Pentium II Xeon
processor system bus agents. For a locked
sequence of transactions, LOCK# is asserted from
the beginning of the first transaction end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for
ownership of the Pentium II Xeon processor system
bus, it will wait until it observes LOCK# deasserted.
This enables symmetric agents to retain ownership of
the Pentium II Xeon processor system bus
throughout the bus locked operation and ensure the
atomicity of lock.
9.1.30.
NMI -
SEE LINT[1]
9.1.31.
PICCLK (I)
The PICCLK (APIC Clock) signal is an input clock to
the processor and core logic or I/O APIC which is
required for operation of all processors, core logic,
and I/O APIC components on the APIC bus. During
FRC mode operation, PICCLK must be 1/4 of (and
synchronous to) BCLK.
9.1.32.
PICD[1:0] (I/O)
The PICD[1:0] (APIC Data) signals are used for bi-
directional serial message passing on the APIC bus,
and must connect the appropriate pins of all
processors and core logic or I/O APIC components
on the APIC bus.
9.1.33.
PRDY# (O)
The PRDY (Probe Ready) signal is a processor
output used by debug tools to determine processor
debug readiness. See Section 8.0. for more
information on this signal.
9.1.34.
PREQ# (I)
The PREQ# (Probe Request) signal is used by
debug tools to request debug operation of the
processors. See Section 8.0. for more information on
this signal.
9.1.34.
PWREN[1:0] (I)
These 2 pins are tied directly together on the
processor. They can be used to detect processor
presence by applying a voltage to one pin and
observing it at the other. See Table 4 for the
maximum rating for this signal.
9.1.35.
PWRGOOD (I)
The PWRGOOD (Power Good) signal is a 2.5 V
tolerant processor input. The processor requires this
signal to be a clean indication that the clocks and
power supplies (V
CCCORE
, V
CCL2
, V
CCTAP
, V
CCSMBus
)
are stable and within their specifications. Clean
implies that the signal will remain low (capable of
sinking leakage current), without glitches, from the
time that the power supplies are turned on until they
come within specification. The signal must then
transition monotonically to a high (2.5 V) state.
Figure 38 illustrates the relationship of PWRGOOD
to other system signals. PWRGOOD can be driven
inactive at any time, but clocks and power must
again be stable before a subsequent rising edge of
PWRGOOD. It must also meet the minimum pulse
width specification in Table 11 and be followed by a
1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the
processor; it is used to protect internal circuits
against voltage sequencing issues. The PWRGOOD
signal does not need to be synchronized for FRC
operation. It should be driven high throughout
boundary scan operation.
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