參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁數(shù)： 25/97頁
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
25
12/15/98 5:14 PM 24377002.doc
Table 11. System Bus AC Specifications (Clock) at the Processor Core
T#
Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
90.00
100.00
MHz
1, 2
T1:
BCLK Period
10.0
11.11
ns
4
3
T2:
BCLK Period Stability
150
ps
4
4, 5, 6
T3:
BCLK High Time
2.5
ns
4
@>2.0 V
T4:
BCLK Low Time
2.5
ns
4
@<0.5 V
T5:
BCLK Rise Time
0.5
1.5
ns
4
(0.5 V–2.0 V)
7
T6:
BCLK Fall Time
0.5
1.5
ns
4
(2.0 V–0.5 V)
7
NOTES:
1.
2.
Table 1 shows the supported ratios for each processor.
Minimum System Bus Frequency is not 100% tested. Specified by design characterization to allow lower speed system
bus operation for up to 6 load systems.
The BCLK period allows a +0.3 ns tolerance for clock driver and routing variation. BCLK must be within specification
whenever PWRGOOD is asserted.
It is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of
10 to 20 pF. Cycle-to-cycle jitter should be measured on adjacent rising edges of BCLK crossing 1.25 V at the processor
core. This cycle-to-cycle jitter present must be accounted for as a component of flight time between the processor(s)
and/or core logic components. Positive or negative jitter of up to 150 ps is allowed between adjacent cycles. Positive or
negative jitter of up to 250 ps is tolerated, but will result in up to 100 ps of AGTL+ I/O and CMOS timing degradation (i.e.,
timing parameters T7-9 and T11-13 will all increase by 100 ps). Thus a system with jitter of 250 ps would need flight times
that are 300 ps (100 ps additional jitter + 100 ps I/O timing degradation for both the source and receiver) better than a
system with jitter of 150 ps.
The clock driver’s closed loop jitter bandwidth should be less than 500 kHz (at -20dB). The bandwidth must be set low to
allow cascade connected PLL-based devices to track clock drivers with the specified jitter. Therefore the bandwidth of the
clock driver’s output frequency-attenuation plot should be less than 500 kHz measured at the -20 dB attenuation point. The
test load should be 10 to 20 pF.
See the 100 MHz 2-Way SMP Pentium
II Xeon Processor/Intel
440GX AGPset AGTL+ Layout Guidelines or the
Pentium
II Xeon Processor/Intel
450NX PCIset AGTL+ Layout Guidelines or additional recommendations.
Not 100% tested. Specified by design characterization as a clock driver requirement.
3.
4.
5.
6.
7.
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