參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 85/97頁(yè)
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
85
12/15/98 5:14 PM 24377002.doc
The ITP565 buffer board drives the TCK signal
through the debug port, to the buffer device.
NOTE
The buffer rise and fall edge rates should
NOT be FASTER than 3 ns. Edge rates
faster than this in the system can
contribute to signal reflections which
endanger ITP compatibility with the target
system.
A low voltage buffer capable of driving
2.5 V outputs such as an 74LVQ244 is
suggested to eliminate the need for
attenuation.
Simulation should be performed to verify
that the edge rates of the buffer chosen are
not too fast.
The pull-up resistor to 2.5 V keeps the TCK signal
from floating when the ITP is not connected. The
value of this resistor should be such that the ITP can
still drive the signal low (1K). The trace lengths from
the buffer to each of the agents should also be kept
at a minimum to ensure good signal integrity.
The “synchronous” mode of the ITP, needed for
debug of FRC pairs, is no longer supported. FRC
mode must be disabled when debugging an FRC-
capable system.
8.1.5.
USING BOUNDARY SCAN TO
COMMUNICATE TO THE PROCESSOR
An ITP communicates to Pentium II Xeon processors
by stopping their execution and sending/receiving
messages over boundary scan pins. As long as each
processor is tied into the system boundary scan
chain, the ITP can communicate with it. In the
simplest case, the processors are back to back in the
scan chain, with the boundary scan input (TDI) of the
first processor connected up directly to the pin
labeled TDI on the debug port and the boundary scan
output of the last processor connected up to the pin
labeled TDO on the debug port as shown in
Figure 37.
8.2.
Integration Tool (Logic
Analyzer) Considerations
8.2.1.
INTEGRATION TOOL MECHANICAL
KEEPOUTS
Designers should also work closely with the vendor
of the LAI that they will be using in debug for
constraints for their tools.
V
CCTAP
Slot 2
Processor
TDI
TDO
Slot 2
Processor
TDI
TDO
Slot 2
Processor
TDI
TDO
Slot 2
Processor
TDI
TDO
TDI
TDO
Debug Port
(ITP)
TDI
TDO
PCIset
Component
TDI
TDO
PCIset
Component
Note: See previous
table for recommended
pull-up resistor values.
3770-37
Figure 37. System Preferred Debug Port Layout
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