參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 81/97頁(yè)
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
81
12/15/98 5:14 PM 24377002.doc
Table 43. Debug Port Pinout Description and Requirements
1
(Continued)
Name
Pin
Description
Specification Requirement
Notes
POWERON
9
Used by ITP to determine
when target system power is
ON and, once target system
is ON, enables all debug port
electrical interface activity.
From target V
TT
to ITP.
Add 1k
pull-up resistor (to
V
TT
)
If no power is applied, the ITP
will not drive any signals;
isolation provided using
isolation gates. Voltage
applied is internally used to
set AGTL+ threshold (or
reference) at 2/3 V
TT
.
TDO
10
Test data output signal from
last component in boundary
scan chain of MP cluster to
ITP; test output is read
serially.
Add 150
pull-up resistor (to
V
CCTAP
)
Design pull-ups to route
around empty processor
sockets (so resistors are not
in parallel)
Operates synchronously with
TCK. Each Pentium II Xeon
processor has a 25
driver.
DBINST#
11
Indicates to target system that
the ITP is installed.
Add ~10k
pull-up resistor
Not required if boundary scan
is not used in target system.
TRST#
12
Test reset signal from ITP to
MP cluster, used to reset TAP
logic.
Add ~680
pull-down
Asynchronous input signal.
To disable TAP reset if ITP
not installed.
BSEN#
14
Informs target system that
ITP is using boundary scan.
Not required if boundary scan
is not used in target system.
PREQ0#
16
PREQ0# signal, driven by
ITP, makes requests to P0 to
enter debug.
Add 150 to 330
pull-up
resistor (to V
CC2.5
)
PRDY0#
18
PRDY0# signal, driven by P0,
informs ITP that P0 is ready
for debug.
Terminate
2
signal properly at
the debug port
Debug port must be at the
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on the ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents if routed properly.
PREQ1#
20
PREQ1# signal from ITP to
P1.
Add 150 to 330
pull-up
resistor (to V
CC2.5
)
PRDY1#
22
PRDY1# signal from P1 to
ITP.
Terminate
2
signal properly at
the debug port
Debug port must be at the
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on the ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents.
PREQ2#
24
PREQ2# signal from ITP to
P2.
Add 150 to 330
pull-up
resistor (to V
CC2.5
)
PRDY2#
26
PRDY2# signal from ITP to
P2 .
Terminate
2
signal properly at
the debug port
Debug port must be at the
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on the ITP
buffer board. Additional load
does not change timing
calculations for the processor
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