參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 39/97頁(yè)
文件大小： 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
39
12/15/98 5:14 PM 24377002.doc
3.
4. All L2 Cache initialization MSRs.
Microcode Update signature resigter, and
4.2.
Low Power States and Clock
Control
The Pentium II Xeon processor allows the use of
Auto HALT, Stop-Grant, and Sleep states to reduce
power consumption by stopping the clock to specific
internal sections of the processor, depending on
each particular state. There is no Deep Sleep state
on the Pentium II Xeon processor. Refer to for the
following sections on low power states for the
Pentium II Xeon processor.
For the processor to fully realize the low current
consumption of the Stop Grant, and Sleep states, an
MSR bit must be set. For the MSR at 02AH (Hex), bit
26 must be set to a ‘1’ (power on default is a ‘0’) for
the processor to stop all internal clocks during these
modes. For more information, see the Pentium
Pro
Processor Family Developer’s Manual
Due to not being able to recognize bus transactions
during Sleep state, SMP systems are not allowed to
have one or more processors in Sleep state and
other processors in Normal or Stop Grant states
simultaneously.
4.2.1.
NORMAL STATE—STATE 1
This is the normal operating state for the processor.
4.2.2.
AUTO HALT POWER DOWN STATE—
STATE 2
Auto HALT is a low power state entered when the
Pentium II Xeon processor executes the HALT
instruction. The processor will issue a normal HALT
bus cycle on BE[7:0]# and REQ[4:0]# when entering
this state. The processor will transition to the Normal
state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# will cause the
processor to immediately initialize itself.
SMI# will cause the processor to execute the SMI
handler. The return from the SMI handler can be to
either Normal Mode or the Auto HALT Power Down
state. See Chapter 11 in the Intel Architecture
Software Developer’s Manual, Volume III: System
Programming Guide
FLUSH# will be serviced during Auto HALT state.
The on-chip first level caches and external second
level cache will be flushed and the processor will
return to the Auto HALT state.
A20M# will be serviced during Auto HALT state; the
processor will mask physical address bit 20 (A20#)
before any look-up in either the on-chip first level
caches or external second level cache, and before a
read/write transaction is driven on the bus.
The system can generate a STPCLK# while the
processor is in the Auto HALT Power Down state.
The processor will generate a Stop Grant bus cycle
when it enters the Stop Grant state from the HALT
state. If the processor enters the Stop Grant state
from the Auto HALT state, the STPCLK# signal must
be deasserted before any interrupts are serviced
(see below). When the system deasserts the
STPCLK# interrupt signal, the processor will return
execution to the HALT state. The processor will not
generate a new HALT bus cycle when it re-enters the
HALT state from the Stop Grant state.
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