參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁(yè)數(shù)： 50/97頁(yè)
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
50
12/16/98 1:29 PM 24377003.doc
Table 34. Thermal Sensor Configuration Register
Bit
Name
Reset State
Function
7 (MSB)
RESERVED
0
Reserved for future use.
6
RUN/STOP
0
Standby mode control bit. If high, the device immediately stops
converting, and enters standby mode. If low, the device converts in
either one-shot mode or automatically updates on a timed basis..
5-0
RESERVED
0
Reserved for future use.
Table 35. Thermal Sensor Conversion Rate Register
Register Contents
Conversion Rate (Hz)
00h
0.0625
01h
0.125
02h
0.25
03h
0.5
04h
1
05h
2
06h
4
07h
8
08h to FFh
Reserved for future use
4.3.6.5.
Conversion Rate Register
The contents of the conversion rate register
determine the nominal rate at which analog to digital
conversions happen when the thermal sensor is in
auto-convert mode. Table 35 shows the mapping
between conversion rate register values and the
conversion rate. As indicated in Table 32, the
conversion rate register is set to its default state of
02h (0.25 Hz nominally) when the thermal sensor is
powered up. There is a ±25% error tolerance
between the conversion rate indicated in the
conversion rate register and the actual conversion
rate.
4.3.7.
SMBUS DEVICE ADDRESSING
Of the addresses broadcast across the SMBus, the
memory components claim those of the form
“1010XXYZb”. The “XX” and “Y” bits are used to
enable the devices on the cartridge at adjacent
addresses. The Y bit is hard-wired on the cartridge to
V
SS
(‘0’) for the Scratch EEPROM and pulled to
V
CCSMBus
(‘1’) for the Processor Information ROM.
The “XX” bits are defined by the processor slot via
the SA0 and SA1 pins on the SC330 connector.
These address pins are pulled down weakly (10k
)
to ensure that the memory components are in a
known state in systems which do not support the
SMBus, or only support a partial implementation. The
“Z” bit is the read/write bit for the serial bus
transaction.
The thermal sensor internally decodes 1 of 3 upper
address patterns from the bus of the form
“0011XXXZb”, “1001XXXZb” or “0101XXXZb”. The
device’s addressing, as implemented, uses SA2 and
SA1 and includes a Hi-Z state for the SA2 address
pin. Therefore the thermal sensor supports 6 unique
resulting addresses. To set the Hi-Z state for SA2,
the pin must be left floating. The system should drive
SA1 and SA0, and will be pulled low (if not driven) by
the 10k
pull-down resistor on the processor
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