參數(shù)資料
型號(hào)： pentium II xeon processor
廠商： Intel Corp.
英文描述： pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
中文描述： 奔騰II至強(qiáng)處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器）
文件頁數(shù)： 21/97頁
文件大?。?/td> 978K
代理商： PENTIUM II XEON PROCESSOR
E
PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
21
12/15/98 5:14 PM 24377002.doc
Table 6. Current Specifications
1
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Icc
CORE
I
CC
for processor core
FMB
1
400 MHz
450 MHz
16.0
12.5 14.0
A
2, 5, 6, 7
Icc
L2
I
CC
for second level cache
FMB
1
400 MHz, 512 KB
400 MHz, 1 MB
450 MHz, 512 KB
450 MHz 1 MB
450MHz 2 MB
9.4
3.0
6.0
3.4
6.8
8.4
A
3, 6, 7
I
VTT
Termination voltage supply current
0
0.3
1.2
A
8
I
SGnt
I
CC
Stop Grant for processor core
0.8
A
6, 9
I
CCSLP
I
CC
Sleep for processor core
0
0.2
A
6
dlcc
CORE
/dt
Core I
CC
slew rate
(at the SC330 connector pins)
20
A/μs
10, 11
dlcc
L2
/dt
Second level cache I
CC
slew rate
(at the SC330 connector pins)
5
A/μs
10, 11
dl
CCVTT
/dt
Termination current slew rate
(at the SC330 connector pins)
5
A/μs
4, 11
I
CCTAP
I
CC
for TAP power supply
100
mA
I
CCSMBus
I
CC
for SMBus power supply
3
10
mA
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. “FMB” is a
suggested design guideline for flexible motherboard design.
I
CCCORE
supplies the processor core.
Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to the
processor.
V
TT
must be held to 1.5 V ±9%. It is recommended that V
TT
be held to 1.5 V ±3% while the Pentium
II Xeon processor
system bus is idle. This is measured at the processor edge fingers.
The typical I
measurements are an average current draw during the execution of Winstone* 96 under the
Windows* 95 operating system. These numbers are meant as a guideline only, not a guaranteed specification. Actual
measurements will vary based upon system environmental conditions and configuration.
Max I
CC
measurements are measured at V
CC
nominal voltage under maximum signal loading conditions.
Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at
maximum current output, is no greater than the nominal (i.e., typical) voltage level of V
CCCORE
(V
CCCORE
). In this
case, the maximum current level for the regulator, I
CCCORE_REG
, can be reduced from the specified maximum current
I
CCCORE MAX
and is calculated by the equation:
CCCORE_REG
= I
CCCORE_MAX
×
V
CCCORE
TYP
/ (V
CCCORE
TYP
+ V
CCCORE
static tolerance)
This is the current required for a single Pentium II Xeon processor. A similar current is drawn through the termination
resistors of each load on the AGTL+ bus. V
TT
is decoupled on the S.E.C. cartridge such that negative current flow due to
the active pull-up to V
CCCORE
in the Pentium II Xeon processor will not be seen at the processor fingers.
The current specified is also for AutoHALT state.
10. Maximum values are specified by design/characterization at nominal V
CC
and at the SC330 connector pins.
11. Based on simulation and averaged over the duration of any change in current. Use to compute the maximum inductance
tolerable and reaction time of the voltage regulator. This parameter is not tested.
2.
3.
4.
5.
6.
7.
8.
9.
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