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| 型號： | pentium II xeon processor |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| 中文描述： | 奔騰II至強處理器400和450兆赫（工作頻率400和450兆赫茲奔二處理器） |
| 文件頁數(shù)： | 26/97頁 |
| 文件大?。?/td> | 978K |
| 代理商： | PENTIUM II XEON PROCESSOR |
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PENTIUM II XEON PROCESSOR AT 400 AND 450 MHZ
E
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12/15/98 5:14 PM 24377002.doc
Table 12. AGTL+ Signal Groups, System Bus AC Specifications at the Processor Core
1
R
L
= 25
Terminated to 1.5 V
T#
Parameter
Min
Max
Unit
Figure
Notes
T7:
AGTL+ Output Valid Delay
0.2
2.7
ns
6
2
T8:
AGTL+ Input Setup Time
1.75
ns
7
3, 4, 5
T9:
AGTL+ Input Hold Time
0.62
ns
7
5
T10:
RESET# Pulse Width
1.00
ms
10
6
NOTES:
1.
2.
These specifications are tested during manufacturing.
Valid delay timings for these signals at the processor core are correlated into 25
termination to 1.5 V and with V
TT
set to
1.5 V.
A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
The signal at the processor core must transition monotonically through the overdrive region (2/3 V
TT
±
200mV).
After the bus ratio on A20M#, IGNNE# and LINT[1:0] are stable, V
CCCORE
, V
CCL2
and BCLK are within specification, and
PWRGOOD is asserted. See Figure 10.
3.
4.
5.
6.
Table 13. CMOS, TAP, Clock and APIC Signal Groups, AC Specifications at the Processor Core
1, 2
T#
Parameter
Min
Max
Unit
Figure
Notes
T11:
CMOS Output Valid Delay
1
8
ns
6
3
T12:
CMOS Input Setup Time
4
ns
7
4, 5
T13:
CMOS Input Hold Time
1
ns
7
4
T14:
CMOS Input Pulse Width, except
PWRGOOD and LINT[1:0]
2
BCLKs
6
Active and Inactive states
T14B: LINT[1:0] Input Pulse Width
6
BCLKs
5
6
T15:
PWRGOOD Inactive Pulse Width
10
BCLKs
6
11
7, 8
NOTES:
1.
2.
3.
4.
5.
6.
These specifications are tested during manufacturing.
These signals may be driven asynchronously but must be driven synchronously in FRC mode.
Valid delay timings for these signals are specified into 100
to 2.5 V.
To ensure recognition on a specific clock, the setup and hold times with respect to BCLK must be met.
INTR and NMI are only valid when the local APIC is disabled. LINT[1:0] are only valid when the local APIC is enabled.
This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an edge triggered
interrupt with fixed delivery, otherwise specification T14 applies.
When driven inactive or after V
CCCORE
, V
CCL2
and BCLK become stable. PWRGOOD must remain below V
IL_MAX
from
Table 8 until all the voltage planes meet the voltage tolerance specifications in Table 5 and BCLK has met the BCLK AC
specifications in Table 11 for at least 10 clock cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
If the BCLK signal meets its AC specification within 150 ns of turning on then the PWRGOOD Inactive Pulse Width
specification is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still remain below V
IL_MAX
until all the voltage planes meet the voltage tolerance specifications.
7.
8.
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