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參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 13/69頁 |
| 文件大小： | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-7-
Pinouts
ISA Bus Control
Signal Name
SA[15:0] /
DD[15:0]
SA16
LA23/DCS3B#,
LA22/DCS1B#,
LA21/DCS3A#,
LA20/DCS1A#,
LA[19:17] /
DA[2:0]
Pin No.
20-25, 27-28,
36-38, 40-44
19
63-67, 69-70
I/O
B
Signal Description
System Address Bus / IDE Data Bus
B
B
System Address Bus
Multifunction Pins
ISA Bus Cycles:
Address: The LA[23:17] address lines are bi-directional. These address lines allow
accesses to physical memory on the ISA bus up to 16MBytes.
PCI IDE Cycles:
Chip Select: DCS1A# is for the ATA command register block and corresponds to
CS1FX# on the primary IDE connector. DCS3A# is for the ATA command register
block and corresponds to CS3FX# on the primary IDE connector. DCS1B# is for the
ATA command register block and corresponds to CS17X# on the primary IDE
connector. DCS3B# is for the ATA command register block and corresponds to
CS37X# on the primary IDE connector.
Disk Address: DA[2:0] are used to indicate which byte in either the ATA command
block or control block is being accessed.
System Data.
SD[15:8] provide the high order byte data path for devices residing on
the ISA bus. These pins also function as
General Purpose Inputs
15-8 if the
GPIO3_CFG bit is low (pin 92 becomes GPI_RE# for enabling external inputs onto
the SD pins using an external buffer). These pins also function as
General Purpose
Outputs
15-8 if the GPIO4_CFG bit is low (pin 136 becomes GPO_WE for control
of an external latch).
System Byte High Enable.
SBHE# indicates, when asserted, that a byte is being
transferred on the upper byte (SD[15:8]) of the data bus. SBHE# is negated during
refresh cycles.
I/O Read.
IOR# is the command to an ISA I/O slave device that the slave may drive
data on to the ISA data bus.
I/O Write.
IOW# is the command to an ISA I/O slave device that the slave may
latch data from the ISA data bus.
Memory Read.
MEMR# is the command to a memory slave that it may drive data
onto the ISA data bus.
Memory Write.
MEMW# is the command to a memory slave that it may latch data
from the ISA data bus.
Standard Memory Read.
SMEMR# is the command to a memory slave, under
1MB, which indicates that it may drive data onto the ISA data bus
Standard Memory Write.
SMEMW# is the command to a memory slave, under
1MB, which indicates that it may latch data from the ISA data bus.
Bus Address Latch Enable.
BALE is an active high signal asserted by the
VT82C586B to indicate that the address (SA[19:0], LA[23:17] and the SBHE#
signal) is valid
16-Bit I/O Chip Select.
This signal is driven by I/O devices on the ISA Bus to
indicate that they support 16-bit I/O bus cycles.
Memory Chip Select 16.
ISA slaves that are 16-bit memory devices drive this line
low to indicate they support 16-bit memory bus cycles.
I/O Channel Check.
When this signal is asserted, it indicates that a parity or an
uncorrectable error has occurred for a device or memory on the ISA Bus.
I/O Channel Ready.
Devices on the ISA Bus negate IOCHRDY to indicate that
additional time (wait states) is required to complete the cycle.
SD[15:8] /
GPI[15:8] /
GPO[15:8]
86-85, 83-80,
78-77
B
SBHE#
62
B
IOR#
12
B
IOW#
11
B
MEMR#
123
B
MEMW#
124
B
SMEMR#
10
O
SMEMW#
9
O
BALE
35
O
IOCS16#
125
I
MEMCS16#
76
I
IOCHCK#
5
I
IOCHRDY
8
I
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