- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359439 > VT82C586B (Electronic Theatre Controls, Inc.) PCI INTEGRATED PERIPHERAL CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 17/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-11-
Pinouts
XD Interface
Signal Name
XD7-0,
EXTSMI7-3#,
GPI7-0,
GPO7-0,
Power-up Straps
Pin No.
122
121
119
118
117
116
114
113
I/O
B
Signal Description
Multifunction Pins
X-bus Data Bus.
For connection to external X-Bus devices (e.g. BIOS ROM)
External SMI Inputs.
External SCI/SMI ports.
General Purpose Inputs.
GPIO3_CFG bit low (pin 92 = GPI_RE#)
General Purpose Outputs.
GPIO4_CFG bit low (pin 136 = GPO_WE)
Power-up Strap Option Inputs.
(see Configuration Register Offset 5Ah)
XD0: 0/1 - Disable/enable internal KBC
XD1: 0/1 - Disable/enable internal PS/2 Mouse
XD2: 0/1 - Disable/enable internal RTC
XD4~XD7: RP13~RP16 for internal KBC
X-Bus Data Direction.
XDIR is tied directly to the direction control of a 74F245
transceiver that buffers the X-Bus data and ISA-Bus data (the output enable of the
transceiver should be grounded). SD0-7 connect to the “A” side of the transceiver
and XD0-7 connect to the “B” side. XDIR high indicates that SD0-7 drives XD0-7.
Multifunction Pin. ROM Chip Select / Keyboard Controller Chip Select.
ISA memory cycle:
ROMCS#.
Chip Select to the BIOS ROM.
ISA I/O cycle:
KBCS#.
Chip Select to the external keyboard controller.
XDIR
112
O
ROMCS# /
KBCS#
135
O
General Purpose I/O
Signal Name
GPIO0 /
EXTSMI0#
Pin No.
94
I/O
B
Signal Description
General Purpose I/O 0
: General Purpose I/O with external SCI/SMI capability.
This pin sits on the VDD-5VSB power plane and is available even under soft-off
state.
General Purpose I/O 1
: General Purpose I/O with external SCI/SMI capability.
Can be used along with pin 88 as an I
2
C pair (by software convention this pin is
defined as clock).
General Purpose I/O 2
: General Purpose I/O with external SCI/SMI capability.
Can be used along with pin 87 as an I
2
C pair (by software convention this pin is
defined as data).
Multifunction Pin
(per GPIO3 Configuration Bit: Function 3 Rx40 bit-6)
GPIO3 Configuration bit high:
General Purpose I/O 3
: General Purpose I/O with
external SCI/SMI capability.
GPIO3 Configuration bit low:
Read Enable for General Purpose Inputs
:
Connects to the output enable (OE# pin) of the external 244 buffers whose data pins
connect to SD15-8 and XD7-0 for GPI15-0.
Multifunction Pin
(per GPIO4 Configuration Bit: Function 3 Rx40 bit-7)
GPIO4 Configuration bit high:
General Purpose I/O 4
: General Purpose I/O with
external SCI/SMI capability.
GPIO4 Configuration bit low:
Write Enable for General Purpose Outputs
:
Connects to the latch enable (LE pin) of the external 373 latches whose data pins
connect to SD15-8 and XD7-0 for GPO15-0.
GPIO1 /
EXTSMI1# /
I2CD1 (Clock)
GPIO2 /
EXTSMI2# /
I2CD2 (Data)
GPIO3 /
EXTSMI3# /
GPI_RE#
87
B
88
B
92
B
GPIO4 /
EXTSMI4# /
GPO_WE
136
B
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VT82C686A | PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER |
| vt82c693 | APOLLO PRO-PLUS |
| VT8371 | KX133 ATHLON NORTH BRIDGE |
| VT83A333 | |
| VT83A334 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VT82C596 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C596A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C596B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C598MVP | 制造商:Via Technologies Inc 功能描述:SYSTEM CONTROLLER, 476 Pin, BGA |
| VT82C686A | 制造商:VIA TECH 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。