
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-
17-
Register Overview
PCI Function 1 Registers - IDE Controller
Configuration Space IDE Header Registers
Offset PCI Configuration Space Header
1-0
Vendor ID
3-2
Device ID
5-4
Command
7-6
Status
8
Revision ID
9
Programming Interface
A
Sub Class Code
B
Base Class Code
C
-reserved- (cache line size)
D
Latency Timer
E
Header Type
F
Built In Self Test (BIST)
13-10 Base Address - Pri Data / Command
17-14 Base Address - Pri Control / Status
1B-18 Base Address - Sec Data / Command
1F-1C Base Address - Sec Control / Status
23-20 Base Address - Bus Master Control
24-2F -reserved- (unassigned)
30-33 -reserved- (expan ROM base addr)
34-3B -reserved- (unassigned)
3C
Interrupt Line
3D
Interrupt Pin
3E
Minimum Grant
3F
Maximum Latency
Default
1106
0571
0080
0280
nn
85
01
01
00
00
00
00
000001F0 RO
000003F4 RO
00000170 RO
00000374 RO
0000CC01
RW
00
00
00
0E
00
00
00
Acc
RO
RO
RO
RW
RO
RW
RO
RO
—
RW
RO
RO
—
—
—
RW
RO
RO
RO
Configuration Space IDE-Specific Registers
Offset Configuration Space IDE Registers
40
Chip Enable
41
IDE Configuration
42
-reserved- (do not program)
43
FIFO Configuration
44
Miscellaneous Control 1
45
Miscellaneous Control 2
46
Miscellaneous Control 3
4B-48 Drive Timing Control
4C
Address Setup Time
4D
-reserved- (do not program)
4E
Sec Non-1F0 Port Access Timing
4F
Pri Non-1F0 Port Access Timing
53-50 UltraDMA33 Extd Timing Control
54-5F -reserved-
61-60 Primary Sector Size
62-67 -reserved-
69-68 Secondary Sector Size
70-FF -reserved-
Default
08
02
09
3A
68
00
C0
A8A8A8A8
RW
FF
00
FF
FF
03030303 RW
00
0200
00
0200
00
Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
—
RW
—
I/O Registers - IDE Controller
These registers are compliant with the SFF 8038 v1.0 standard.
Refer to that specification for additional information.
Offset IDE I/O Registers
0
Primary Channel Command
1
-reserved-
2
Primary Channel Status
3
-reserved-
4-7
Primary Channel PRD Table Addr
8
Secondary Channel Command
9
-reserved-
A
Secondary Channel Status
B
-reserved-
C-F
Secondary Channel PRD Table Addr
Default
00
00
00
00
00
00
00
00
00
00
Acc
RW
—
WC
—
RW
RW
—
WC
—
RW