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參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 59/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
53-
Register Descriptions
General Purpose I/O Registers
Offset 40 - GPIO Direction Control (GPIO_DIR) ......... RW
7
Reserved
..........................................always read 0
6
SMI/SCI Event Disable on GPIO3/GPIO4
0
Enable GPIO3/GPIO4 to cause SCI/SMI
Events.....................................................default
1
GPIO3/GPIO4 will only cause SCI/SMI
Events during Power-On-Suspend (POS) mode
5
Interrupt Resume from Power-On Suspend
0
Enable (resume on interrupt from POS)...... def
1
Disable (ignore interrupts during POS)
4
GPIO4_DIR
0
Pin 136 is GPIO4 input..........................default
1
Pin 136 is GPIO4 output (if Rx40 bit-7 = 1)
If Rx40[7]=0 (PCI Configuration function 3 offset
40h GPIO4_CFG bit), pin 136 is the GPO_WE
output, independent of the state of this bit.
3
GPIO3_DIR
0
Pin 92 is GPIO3 input............................default
1
Pin 92 is GPIO3 output (if Rx40 bit-6 = 1)
If Rx40[6]=0 (PCI Configuration function 3 offset
40h GPIO3_CFG bit), pin 92 is the GPI_RE# output,
independent of the state of this bit.
2
GPIO2_DIR
0
Pin 88 is GPIO2 / I2CD1 input ..............default
1
Pin 88 is GPIO2 / I2CD1 output
1
GPIO1_DIR
0
Pin 87 is GPIO1 / I2CD2 input ..............default
1
Pin 87 is GPIO1 / I2CD2 output
0
GPIO0_DIR
0
Pin 94 is GPIO0 input............................default
1
Pin 94 is GPIO0 output
Offset 42 - GPIO Port Output Value (GPIO_VAL) ...... RW
7-5
Reserved
........................................always reads 0
4
GPIO4_VAL
Write output value for the GPIO4 pin if the port is
available (GPIO4_CFG = 1 in PCI Config Register
function 3 offset 40h). The input state of the GPIO4
pin may be read from register EXTSMI_VAL bit-4.
3
GPIO3_VAL
Write output value for the GPIO3 pin if the port is
available (GPIO3_CFG = 1 in PCI Config Register
function 3 offset 40h). The input state of the GPIO3
pin may be read from register EXTSMI_VAL bit-3.
2
GPIO2_VAL
Write output value for the GPIO2 (I2CD2) pin. The
input state of the GPIO2 pin may be read from
register EXTSMI_VAL bit-2.
1
GPIO1_VAL
Write output value for the GPIO1 (I2CD1) pin. The
input state of the GPIO1 pin may be read from
register EXTSMI_VAL bit-1.
0
GPIO0_VAL
Write output value for the GPIO0 pin. The input
state of the GPIO0 pin may be read from register
EXTSMI_VAL bit-0.
Offset 44 - GPIO Port Input Value (EXTSMI_VAL) .... RO
Depending on the configuration, up to 8 external SCI/SMI
ports are available as indicated below. The state of these
inputs may be read in this register.
7
EXTSMI7# Input Value
GPIO3_CFG=0: EXTSMI7# on XD7 (pin 122)
GPIO3_CFG=1: EXTSMI7# function not available
6
EXTSMI6# Input Value
GPIO3_CFG=0: EXTSMI6# on XD6 (pin 121)
GPIO3_CFG=1: EXTSMI6# function not available
5
EXTSMI5# Input Value
GPIO3_CFG=0: EXTSMI5# on XD5 (pin 119)
GPIO3_CFG=1: EXTSMI5# function not available
4
EXTSMI4# Input Value
GPIO4_CFG=0:
GPIO3_CFG=0: EXTSMI4# on XD4 (pin 118)
GPIO3_CFG=1: EXTSMI4# function not avail
GPIO4_CFG=1: EXTSMI4# on GPIO4 (pin 136)
3
EXTSMI3# Input Value
GPIO3_CFG=0: EXTSMI3# on XD3 (pin 117)
GPIO3_CFG=1: EXTSMI3# on GPIO3 (pin 92)
2
EXTSMI2# Input Value
(on GPIO2 pin 88)
1
EXTSMI1# Input Value
(on GPIO1 pin 87)
0
EXTSMI0# Input Value
(on GPIO0 pin 94)
Note: GPIO3_CFG and GPIO4_CFG are located in PCI
Configuration Register function 3 offset 40h.
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