參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁(yè)數(shù)： 48/69頁(yè)
文件大?。?/td> 393K
代理商： VT82C586B
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VT82C586B
Revision 1.0
May 13, 1997
-
42-
Register Descriptions
Offset 53-50 - GP Timer Control (0000 0000h) .............. RW
31-30 Conserve Mode Timer Count Value
00 1/16 second ............................................default
01 1/8 second
10 1 second
11 1 minute
29
Conserve Mode Status
This bit reads 1 when in Conserve Mode
28
Conserve Mode Enable
Set to 1 to enable Conserve Mode (not used in
desktop applications).
27-26 Secondary Event Timer Count Value
00 2 milliseconds.........................................default
01 64 milliseconds
10 second
11 by EOI + 0.25 milliseconds
25
Secondary Event Occurred Status
This bit reads 1 to indicate that a secondary event has
occurred (to resume the system from suspend) and the
secondary event timer is counting down.
24
Secondary Event Timer Enable
0
Disable ...................................................default
1
Enable
23-16 GP1 Timer Count Value
(base defined by bits 5-4)
15-8 GP0 Timer Count Value
(base defined by bits 1-0)
7
GP1 Timer Start
On setting this bit to 1, the GP1 timer loads the value
defined by bits 23-16 of this register and starts
counting down. The GP1 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP
Timer
Reload
Enable
Management I/O Space Offset 38h). If no such event
occurs and the GP1 timer counts down to zero, then
the GP1 Timer Timeout Status bit is set to one (bit-3
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP1 Timer Timeout Enable bit is set (bit-3 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
GP1 Timer Automatic Reload
This bit is set to one to enable the GP1 timer to reload
automatically after counting down to 0.
GP1 Timer Base
00 Disable ...................................................default
01 32 usec
10 1 second
11 1 minute
Register
(Power
6
5-4
3
GP0 Timer Start
On setting this bit to 1, the GP0 timer loads the value
defined by bits 15-8 of this register and starts
counting down. The GP0 timer is reloaded at the
occurrence of certain peripheral events enabled in the
GP
Timer
Reload
Enable
Management I/O Space Offset 38h). If no such event
occurs and the GP0 timer counts down to zero, then
the GP0 Timer Timeout Status bit is set to one (bit-2
of the Global Status register at Power Management
Register I/O Space Offset 28h). Additionally, if the
GP0 Timer Timeout Enable bit is set (bit-2 of the
Global Enable register at Power Management
Register I/O Space Offset 2Ah), then an SMI is
generated.
GP0 Timer Automatic Reload
This bit is set to one to enable the GP0 timer to reload
automatically after counting down to 0.
GP0 Timer Base
00 Disable...................................................default
01 1/16 second
10 1 second
11 1 minute
Register
(Power
2
1-0
Offset 61 - Programming Interface Read Value ............ WO
7-0
Rx09 Read Value
The value returned by the register at offset 9h (Programming
Interface) may be changed by writing the desired value to this
location.
Offset 62 - Sub Class Read Value .................................... WO
7-0
Rx0A Read Value
The value returned by the register at offset 0Ah (Sub Class
Code) may be changed by writing the desired value to this
location.
Offset 63 - Base Class Read Value .................................. WO
7-0
Rx0B Read Value
The value returned by the register at offset 0Bh (Base Class
Code) may be changed by writing the desired value to this
location.
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