- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359439 > VT82C586B (Electronic Theatre Controls, Inc.) PCI INTEGRATED PERIPHERAL CONTROLLER PDF資料下載
參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 55/69頁 |
| 文件大小： | 393K |
| 代理商： | VT82C586B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
9,$7HFKQRORJLHV,QF
VT82C586B
Revision 1.0
May 13, 1997
-
49-
Register Descriptions
General Purpose Power Management Registers
Offset 21-20 - General Purpose Status (GP_STS) ....... RWC
15-10 Reserved
........................................ always reads 0
9
USB Resume Status (USB_STS)
This bit is set when a USB peripheral generates a
resume event.
8
Ring Status (RI_STS)
This bit is set when the RI# input is asserted low.
7
EXTSMI7 Toggle Status (EXT7_STS)
This bit is set when the EXTSMI7# pin is toggled.
6
EXTSMI6 Toggle Status (EXT6_STS)
This bit is set when the EXTSMI6# pin is toggled.
5
EXTSMI5 Toggle Status (EXT5_STS)
This bit is set when the EXTSMI5# pin is toggled.
4
EXTSMI4 Toggle Status (EXT4_STS)
This bit is set when the EXTSMI4# pin is toggled.
3
EXTSMI3 Toggle Status (EXT3_STS)
This bit is set when the EXTSMI3# pin is toggled.
2
EXTSMI2 Toggle Status (EXT2_STS)
This bit is set when the EXTSMI2# pin is toggled.
1
EXTSMI1 Toggle Status (EXT1_STS)
This bit is set when the EXTSMI1# pin is toggled.
0
EXTSMI0 Toggle Status (EXT0_STS)
This bit is set when the EXTSMI0# pin is toggled.
Note that the above bits correspond one for one with the bits
of the General Purpose SCI Enable and General Purpose SMI
Enable registers at offsets 22 and 24: an SCI or SMI is
generated if the corresponding bit of the General Purpose SCI
or SMI Enable registers, respectively, is set to one.
The above bits are set by hardware only and can only be
cleared by writing a one to the desired bit.
Offset 23-22 - General Purpose SCI Enable ................... RW
15-10 Reserved
........................................always reads 0
9
Enable SCI on setting of the USB_STS bit
....def=0
8
Enable SCI on setting of the RI_STS bit
.......def=0
7
Enable SCI on setting of the EXT7_STS bit
..def=0
6
Enable SCI on setting of the EXT6_STS bit
..def=0
5
Enable SCI on setting of the EXT5_STS bit
..def=0
4
Enable SCI on setting of the EXT4_STS bit
..def=0
3
Enable SCI on setting of the EXT3_STS bit
..def=0
2
Enable SCI on setting of the EXT2_STS bit
..def=0
1
Enable SCI on setting of the EXT1_STS bit
..def=0
0
Enable SCI on setting of the EXT0_STS bit
..def=0
These bits allow generation of an SCI using a separate set of
conditions from those used for generating an SMI.
Offset 25-24 - General Purpose SMI Enable .................. RW
15-10 Reserved
........................................always reads 0
9
Enable SMI on setting of the USB_STS bit
...def=0
8
Enable SMI on setting of the RI_STS bit
......def=0
7
Enable SMI on setting of the EXT7_STS bit
..def=0
6
Enable SMI on setting of the EXT6_STS bit
..def=0
5
Enable SMI on setting of the EXT5_STS bit
..def=0
4
Enable SMI on setting of the EXT4_STS bit
..def=0
3
Enable SMI on setting of the EXT3_STS bit
..def=0
2
Enable SMI on setting of the EXT2_STS bit
..def=0
1
Enable SMI on setting of the EXT1_STS bit
..def=0
0
Enable SMI on setting of the EXT0_STS bit
..def=0
These bits allow generation of an SMI using a separate set of
conditions from those used for generating an SCI.
Offset 27-26 - Power Supply Control .............................. RW
15-11 Reserved
........................................always reads 0
10
Ring PS Control (RI_PS_CTL)
......................def=0
This bit enables the setting of the RI_STS bit to turn
on the VDD_5V power plane by setting PWRON = 1.
9
Power Button Control (PB_CTL)
..................def=1
This bit is used to control the setting of the PB_STS
bit to resume the system from suspend (turn on the
VDD_5V power plane by setting PWRON = 1).
8
RTC PS Control (RTC_PS_CTL)
..................def=0
This bit enables the setting of the RTC_STS bit to
resume the system from suspend (turn on the
VDD_5V power plane by setting PWRON = 1).
7-1
Reserved
........................................always reads 0
0
EXTSMI0 Toggle PS Control (E0_PS_CTL)
def=0
This bit enables the setting of the EXT0_STS bit to
resume the system from suspend (turn on the
VDD_5V power plane by setting PWRON = 1).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VT82C686A | PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER |
| vt82c693 | APOLLO PRO-PLUS |
| VT8371 | KX133 ATHLON NORTH BRIDGE |
| VT83A333 | |
| VT83A334 | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VT82C596 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C596A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C596B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI INTEGRATED PERIPHERAL CONTROLLER |
| VT82C598MVP | 制造商:Via Technologies Inc 功能描述:SYSTEM CONTROLLER, 476 Pin, BGA |
| VT82C686A | 制造商:VIA TECH 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。