參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁(yè)數(shù)： 47/69頁(yè)
文件大小： 393K
代理商： VT82C586B
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VT82C586B
Revision 1.0
May 13, 1997
-
41-
Register Descriptions
Power Management-Specific PCI Configuration Registers
Offset 40 - Pin Configuration (C0h) ................................ RW
7
GPIO4 Configuration
0
Define pin 136 as GPO_WE
1
Define pin 136 as GPIO4.......................default
6
GPIO3 Configuration
0
Define pin 92 as GPI_RE#
1
Define pin 92 as GPIO4.........................default
5-0
Reserved
........................................ always reads 0
Offset 41 - General Configuration (00h) ......................... RW
7
3040E and earlier: Reserved
7
3040F and later: I/O Enable for ACPI I/O Base
0
Disable access to ACPI I/O block..........default
1
Allow access to Power Management I/O
Register Block (see offset 4B-48 to set the
base address for this register block). The
definitions of the registers in the Power
Management I/O Register Block are included
later in this document, following the Power
Management Subsystem overview.
6
ACPI Timer Reset
0
Disable ...................................................default
1
Enable
5-4
Reserved
(Do Not Program)...................... default = 0
3
ACPI Timer Count Select
0
24-bit Timer ...........................................default
1
32-bit Timer
2
PCI Frame Activation in C2 as Resume Event
0
Disable ...................................................default
1
Enable
1
Clock Throttling Clock Selection
0
32 usec (512 usec cycle time).................default
1
1 msec (16 msec cycle time)
0
Reserved
(Do Not Program)...................... default = 0
Offset 42 - SCI Interrupt Configuration (00h) ............... RW
7-4
Reserved
........................................ always reads 0
3-0
SCI Interrupt Assignment
0000 Disabled .................................................default
0001 IRQ1
0010 Reserved
0011 IRQ3
0100 IRQ4
0101 IRQ5
0110 IRQ6
0111 IRQ7
1000 IRQ8
1001 IRQ9
1010 IRQ10
1011 IRQ11
1100 IRQ12
1101 IRQ13
1110 IRQ14
1111 IRQ15
Offset 45-44 - Primary Interrupt Channel (0000h) ....... RW
15
1/0 = Ena/Disa IRQ15 as Primary Intrpt Channel
14
1/0 = Ena/Disa IRQ14 as Primary Intrpt Channel
13
1/0 = Ena/Disa IRQ13 as Primary Intrpt Channel
12
1/0 = Ena/Disa IRQ12 as Primary Intrpt Channel
11
1/0 = Ena/Disa IRQ11 as Primary Intrpt Channel
10
1/0 = Ena/Disa IRQ10 as Primary Intrpt Channel
9
1/0 = Ena/Disa IRQ9 as Primary Intrpt Channel
8
1/0 = Ena/Disa IRQ8 as Primary Intrpt Channel
7
1/0 = Ena/Disa IRQ7 as Primary Intrpt Channel
6
1/0 = Ena/Disa IRQ6 as Primary Intrpt Channel
5
1/0 = Ena/Disa IRQ5 as Primary Intrpt Channel
4
1/0 = Ena/Disa IRQ4 as Primary Intrpt Channel
3
1/0 = Ena/Disa IRQ3 as Primary Intrpt Channel
2
Reserved
........................................always reads 0
1
1/0 = Ena/Disa IRQ1 as Primary Intrpt Channel
0
1/0 = Ena/Disa IRQ0 as Primary Intrpt Channel
Offset 47-46 - Secondary Interrupt Channel (0000h) .... RW
15
1/0 = Ena/Disa IRQ15 as Secondary Intr Channel
14
1/0 = Ena/Disa IRQ14 as Secondary Intr Channel
13
1/0 = Ena/Disa IRQ13 as Secondary Intr Channel
12
1/0 = Ena/Disa IRQ12 as Secondary Intr Channel
11
1/0 = Ena/Disa IRQ11 as Secondary Intr Channel
10
1/0 = Ena/Disa IRQ10 as Secondary Intr Channel
9
1/0 = Ena/Disa IRQ9 as Secondary Intr Channel
8
1/0 = Ena/Disa IRQ8 as Secondary Intr Channel
7
1/0 = Ena/Disa IRQ7 as Secondary Intr Channel
6
1/0 = Ena/Disa IRQ6 as Secondary Intr Channel
5
1/0 = Ena/Disa IRQ5 as Secondary Intr Channel
4
1/0 = Ena/Disa IRQ4 as Secondary Intr Channel
3
1/0 = Ena/Disa IRQ3 as Secondary Intr Channel
2
Reserved
........................................always reads 0
1
1/0 = Ena/Disa IRQ1 as Secondary Intr Channel
0
1/0 = Ena/Disa IRQ0 as Secondary Intr Channel
Offset 4B-48 - I/O Register Base Address (3040F and later
silicon; see Offset 23-20 for 3040E and earlier) ............ RW
31-16 Reserved
........................................always reads 0
15-8 Power Management I/O Register Base Address.
Port Address for the base of the 256-byte Power
Management I/O Register block, corresponding to
AD[15:8]. The "I/O Space" bit at offset 41 bit-7
(offset 5-4 bit-0 in 3040E and earlier silicon) enables
access to this register block. The definitions of the
registers in the Power Management I/O Register
Block are included later in this document, following
the Power-Management-Specific PCI Configuration
register descriptions and the Power Management
Subsystem overview.
7-0
00000001b
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