參數(shù)資料
型號(hào)： VT82C586B
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述： 整合的周邊控制器的PCI
文件頁(yè)數(shù)： 34/69頁(yè)
文件大?。?/td> 393K
代理商： VT82C586B
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VT82C586B
Revision 1.0
May 13, 1997
-
28-
Register Descriptions
Offset 42 - ISA Clock Control. ......................................... RW
7
Latch IO16#
0
Enable (recommended setting)...............default
1
Disable
6
Reserved
(no defined function)................. default = 0
5
Master Request Test Mode
(do not program) .def=0
4
Reserved
(no defined function)................. default = 0
3
ISA CLOCK Select Enable
0
ISA Clock = PCICLK/4 .........................default
1
ISA Clock selected per bits 2-0
2-0
ISA Bus Clock Select
(if bit-3 = 1)
000 PCICLK/3 ..............................................default
001 PCICLK/2
010 PCICLK/4
011 PCICLK/6
100 PCICLK/5
101 PCICLK/10
110 PCICLK/12
111 OSC/2
Note: Procedure for ISA CLOCK switching:
1) Set bit 3 to 0; 2) Change value of bit 2-0; 3) Set bit 3 to 1
Offset 43 - ROM Decode Control .................................... RW
Setting these bits enables the indicated address range to be
included in the ROMCS# decode:
7
FFFE0000h-FFFEFFFFh
.......................... default=0
6
FFF80000h-FFFDFFFFh
......................... default=0
5
000E8000h-000EFFFFh
............................ default=0
4
000E0000h-000E7FFFh
............................ default=0
3
000D8000h-000DFFFFh
........................... default=0
2
000D0000h-000D7FFFh
............................ default=0
1
000C8000h-000CFFFFh
........................... default=0
0
000C0000h-000C7FFFh
............................. default=0
Offset 44 - Keyboard Controller Control ....................... RW
7
KBC Timeout Test
(do not program)....... default = 0
6-4
Reserved
(do not program)........................ default = 0
3
Mouse Lock Enable
0
Disabled .................................................default
1
Enabled
2-1
Reserved
(do not program)........................ default = 0
0
Reserved
(no function).............................. default = 0
Offset 45 - Type F DMA Control ..................................... RW
7
ISA Master / DMA to PCI Line Buffer
.... default=0
6
DMA type F Timing on Channel 7
........... default=0
5
DMA type F Timing on Channel 6
........... default=0
4
DMA type F Timing on Channel 5
........... default=0
3
DMA type F Timing on Channel 3
........... default=0
2
DMA type F Timing on Channel 2
........... default=0
1
DMA type F Timing on Channel 1
........... default=0
0
DMA type F Timing on Channel 0
........... default=0
Offset 46 - Miscellaneous Control 1 ................................ RW
7
PCI Master Write Wait States.(3041 Silicon Only)
0
0 Wait States..........................................default
1
1 Wait State
6
Gate INTRQ...............................(3041 Silicon Only)
0
Disable...................................................default
1
Enable
5
Flush Line Buffer for Int or DMA IOR Cycle........
...............................(3041 Silicon Only)
0
Disable...................................................default
1
Enable
4
Config Command Reg Rx04 Access (Test Only)
0
Normal: Bits 0-1=RO, Bit 3=RW.........default
1
Test Mode: Bits 0-1=RW, Bit-3=RO
3
Reserved
(do not program)........................default = 0
2
Reserved
(no function) ..............................default = 0
1
PCI Burst Read Interruptability
0
Allow burst reads to be interrupted........default
1
Don’t allow PCI burst reads to be interrupted
0
Post Memory Write Enable
0
Disable...................................................default
1
Enable
The Post Memory Write function is automatically
enabled when Delay Transaction (see Rx47 bit-6
below) is enabled, independent of the state of this bit.
Offset 47 - Miscellaneous Control 2 ................................ RW
7
CPU Reset Source
0
Use CPURST as CPU Reset..................default
1
Use INIT as CPU Reset
6
PCI Delay Transaction Enable
0
Disable...................................................default
1
Enable
The "Post Memory Write" function is automatically
enabled when this bit is enabled, independent of the
state of Rx46 bit-0 above.
5
EISA 4D0/4D1 Port Enable
0
Disable (ignore ports 4D0-1).................default
1
Enable (ports 4D0-1 per EISA specification)
4
Interrupt Controller Shadow Register Enable
0
Disable...................................................default
1
Enable
3
Reserved (always program to 0)
..............default = 0
Note: Always mask this bit. This bit may read back
as either 0 or 1 but must always be
programmed with 0.
2
Write Delay Transaction Time-Out Timer Enable
0
Disable...................................................default
1
Enable
1
Read Delay Transaction Time-Out Timer Enable
0
Disable...................................................default
1
Enable
0
Software PCI Reset
......write 1 to generate PCI reset
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