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參數(shù)資料
| 型號(hào)： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁(yè)數(shù)： | 20/69頁(yè) |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
14-
Register Overview
R
EGISTERS
Register Overview
The following tables summarize the configuration and I/O
registers of the VT82C586B. These tables also document the
power-on default value (“Default”) and access type (“Acc”) for
each register. Access type definitions used are RW
(Read/Write), RO (Read/Only), “—” for reserved / used
(essentially the same as RO), and RWC (or just WC) (Read /
Write 1’s to Clear individual bits). Registers indicated as RW
may have some read/only bits that always read back a fixed
value (usually 0 if unused); registers designated as RWC or
WC may have some read-only or read write bits (see individual
register descriptions for details).
Detailed register descriptions are provided in the following
section of this document. All offset and default values are
shown in hexadecimal unless otherwise indicated
Table 2. System I/O Map
Port
00-1F
Function
Master DMA Controller
Actual Port Decoding
0000 0000 000x nnnn
20-3F
Master Interrupt Controller 0000 0000 001x xxxn
40-5F
Timer / Counter
0000 0000 010x xxnn
60-6F
(60h)
(61h)
(64h)
Keyboard Controller
KBC Data
Misc Functions & Spkr Ctrl 0000 0000 0110 xxx1
KBC Command / Status
0000 0000 0110 xnxn
0000 0000 0110 x0x0
0000 0000 0110 x1x0
70-77
78-7F
RTC/CMOS/NMI-Disable 0000 0000 0111 0nnn
-available for system use-
0000 0000 0111 1xxx
80
81-8F
-reserved- (debug port)
DMA Page Registers
0000 0000 1000 0000
0000 0000 1000 nnnn
90-91
92
93-9F
-available for system use-
System Control
-available for system use-
0000 0000 1001 000x
0000 0000 1001 0010
0000 0000 1001 nnnn
A0-BF
Slave Interrupt Controller
0000 0000 101x xxxn
C0-DF
Slave DMA Controller
0000 0000 110n nnnx
E0-FF
-available for system use-
0000 0000 111x xxxx
100-CF7
-available for system use-
CF8-CFB
CFC-CFF
PCI Configuration Address 0000 1100 1111 10xx
PCI Configuration Data
0000 1100 1111 11xx
D00-FFFF -available for system use-
Table 3. Registers
Legacy I/O Registers
Port
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
Master DMA Controller Registers
Channel 0 Base & Current Address
Channel 0 Base & Current Count
Channel 1 Base & Current Address
Channel 1 Base & Current Count
Channel 2 Base & Current Address
Channel 2 Base & Current Count
Channel 3 Base & Current Address
Channel 3 Base & Current Count
Status / Command
Write Request
Write Single Mask
Write Mode
Clear Byte Pointer FF
Master Clear
Clear Mask
Read / Write Mask
Default Acc
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
WO
WO
WO
WO
WO
RW
Port
20
21
20
21
* RW if shadow registers are disabled
Master Interrupt Controller Regs
Master Interrupt Control
Master Interrupt Mask
Master Interrupt Control Shadow
Master Interrupt Mask Shadow
Default Acc
—
—
—
—
*
*
RW
RW
Port
40
41
42
43
Timer/Counter Registers
Timer / Counter 0 Count
Timer / Counter 1 Count
Timer / Counter 2 Count
Timer / Counter Control
Default Acc
RW
RW
RW
WO
Port
60
61
64
Keyboard Controller Registers
Keyboard Controller Data
Misc Functions & Speaker Control
Keyboard Ctrlr Command / Status
Default Acc
RW
RW
RW
Port
70
71
72
73
74
75
NMI Disable is port 70h (CMOS Memory Address) bit-7.
RTC control occurs via specific CMOS data locations (0-0Dh).
Ports 72-73 may be used to access all 256 locations of CMOS.
Ports 74-75 may be used to access CMOS if the internal RTC is
disabled.
CMOS / RTC / NMI Registers
CMOS Memory Address & NMI Disa
CMOS Memory Data (128 bytes)
CMOS Memory Address
CMOS Memory Data (256 bytes)
CMOS Memory Address
CMOS Memory Data (256 bytes)
Default Acc
WO
RW
RW
RW
RW
RW
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