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參數(shù)資料
| 型號(hào)： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 57/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
51-
Register Descriptions
Offset 2D-2C - Global Control (GBL_CTL) ................... RW
15-9 Reserved
........................................ always reads 0
8
SMI Active (INSMI)
0
SMI Inactive...........................................default
1
SMI Active. If the SMIIG bit is set, this bit
needs to be written with a 1 to clear it before
the next SMI can be generated.
7-5
Reserved
........................................ always reads 0
4
SMI Lock (SMIIG)
0
Disable SMI Lock..................................default
1
Enable SMI Lock (SMI low to gate for the
next SMI).
3
Reserved
........................................ always reads 0
2
Power Button Triggering
0
SCI/SMI generated by PWRBTN# low level
1
SCI/SMI generated by PWRBTN# rising edge
Set to one to avoid the situation where PB_STS is set
to wake up the system then reset again by
PBOR_STS to switch the system into the soft-off
state. Must be set to 0 for ACPI v0.9 compliance.
1
BIOS Release (BIOS_RLS)
This bit is set by legacy software to indicate release
of the SCI/SMI lock. Upon setting of this bit,
hardware automatically sets the GBL_STS bit. This
bit is cleared by hardware when the GBL_STS bit
cleared by software.
Note that if the GBL_EN bit is set (bit-5 of the Power
Management Enable register at offset 2), then setting
this bit causes an SCI to be generated (because setting
this bit causes the GBL_STS bit to be set).
0
SMI Enable (SMI_EN)
0
Disable all SMI generation
1
Enable SMI generation
Offset 2F - SMI Command (SMI_CMD) ............. 3041: RW
............... 3040: WO, always reads 0 (Read at Func 3 Rx47)
7-0
SMI Command
Writing to this port sets the SW_SMI_STS bit. Note
that if the SW_SMI_EN bit is set (see bit-6 of the
Global Enable register at offset 2Ah), then an SMI is
generated.
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