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參數(shù)資料
| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 37/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
31-
Register Descriptions
Offset 5A - XD Power-On Strap Options ........................ RW
The bits in this register are latched from pins XD7-0 at power-
up but are read/write accessible so may be changed after
power-up to change the default strap setting:
7
6
5
4
3
2
Keyboard RP16
.............................latched from XD7
Keyboard RP15
............................latched from XD6
Keyboard RP14
............................latched from XD5
Keyboard RP13
............................latched from XD4
Reserved
....................................... always reads 0
Internal RTC Enable
....................latched from XD2
0
Disable
1
Enable
Internal PS2 Mouse Enable
..........latched from XD1
0
Disable
1
Enable
Internal KBC Enable
....................latched from XD0
0
Disable
1
Enable
1
0
Note:
External strap option values may be set by connecting
the indicated external pin to a 4.7K ohm pullup (for
1) or driving it low during reset with a 7407 TTL
open collector buffer (for 0) as shown in the
suggested circuit below:
9&&
.
;'
5(6(7
9&&
Figure 3. Strap Option Circuit
Offset 5B - Internal RTC Test Mode .............................. RW
7-3
Reserved
........................................always reads 0
2
RTC Reset Enable
(do not program)..........default=0
1
RTC SRAM Access Enable
0
Disable...................................................default
1
Enable
This bit is set if the internal RTC is disabled but it is
desired to still be able to access the internal RTC
SRAM via ports 74-75. If the internal RTC is
enabled, setting this bit does nothing (the internal
RTC SRAM should be accessed at either ports 70/71
or 72/73.
0
RTC Test Mode Enable
(do not program) .default=0
Offset 5C - DMA Control (3041 Silicon Only) ............... RW
7-1
Reserved
........................................always reads 0
0
DMA Line Buffer Disable
0
DMA cycles can be to/from line buffer .......def
1
Disable DMA Line Buffer
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