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您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359439 > VT82C586B (Electronic Theatre Controls, Inc.) PCI INTEGRATED PERIPHERAL CONTROLLER PDF資料下載

參數(shù)資料

型號：	VT82C586B
廠商：	Electronic Theatre Controls, Inc.
英文描述：	PCI INTEGRATED PERIPHERAL CONTROLLER
中文描述：	整合的周邊控制器的PCI
文件頁數(shù)：	56/69頁
文件大小：	393K
代理商：	VT82C586B

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VT82C586B

Revision 1.0

May 13, 1997

50-

Generic Power Management Registers

Offset 29-28 - Global Status .......................................... RWC

15-7 Reserved

........................................ always reads 0

Software SMI Status (SW_SMI_STS)

............def=0

This bit is set when the SMI_CMD port (offset 2F) is

written.

BIOS Status (BIOS_STS)

................................def=0

This bit is set when the GBL_RLS bit is set to one

(typically by the ACPI software to release control of

the SCI/SMI lock). When this bit is reset (by writing

a one to this bit position) the GBL_RLS bit is reset at

the same time by hardware.

Legacy USB Status (LEG_USB_STS)

............def=0

This bit is set when a legacy USB event occurs.

GP1 Timer Time Out Status (GP1TO_STS)

..def=0

This bit is set when the GP1 timer times out.

GP0 Timer Time Out Status (GP0TO_STS)

..def=0

This bit is set when the GP0 timer times out.

Secondary Event Timer Time Out Status

(STTO_STS)

.....................................................def=0

This bit is set when the secondary event timer times

out.

Primary Activity Status (PACT_STS)

............def=0

This bit is set at the occurrence of any enabled

primary system activity (see the Primary Activity

Detect Status register at offset 30h and the Primary

Activity Detect Enable register at offset 34h). After

checking this bit, software can check the status bits in

the Primary Activity Detect Status register at offset

30h to identify the specific source of the primary

event. Note that setting this bit can be enabled to

reload the GP0 timer (see bit-0 of the GP Timer

Reload Enable register at offset 38).

Note that SMI can be generated based on the setting of any of

the above bits (see the offset 2Ah Global Enable register bit

descriptions in the right hand column of this page).

The bits in this register are set by hardware only and can only

be cleared by writing a one to the desired bit position.

Offset 2B-2A - Global Enable .......................................... RW

15-7 Reserved

........................................always reads 0

Software SMI Enable (SW_SMI_EN)

............def=0