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| 型號： | VT82C586B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI INTEGRATED PERIPHERAL CONTROLLER |
| 中文描述： | 整合的周邊控制器的PCI |
| 文件頁數(shù)： | 41/69頁 |
| 文件大?。?/td> | 393K |
| 代理商： | VT82C586B |
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VT82C586B
Revision 1.0
May 13, 1997
-
35-
Register Descriptions
IDE-Controller-Specific Confiiguration Registers
Offset 40 - Chip Enable .................................................... RW
7-2
Reserved
............................ always reads 000001b
1
Primary Channel Enable
........ default = 0 (disabled)
0
Secondary Channel Enable
.... default = 0 (disabled)
Offset 41 - IDE Configuration ......................................... RW
7
Primary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
6
Primary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
5
Secondary IDE Read Prefetch Buffer
0
Disable ...................................................default
1
Enable
4
Secondary IDE Post Write Buffer
0
Disable ...................................................default
1
Enable
3
Reserved (read write)
.......
do not change
, default=0
2
Reserved (read write)
.......
do not change
, default=1
1
Reserved (read write)
.......
do not change
, default=1
0
Reserved (read write)
.......
do not change
, default=0
Offset 42 - Reserved (Do Not Program) .......................... RW
Offset 43 - FIFO Configuration ....................................... RW
7
PREQ# Asserted Till DDACK# De-Asserted ..........
.............................. (3041 Silicon Only)
0
Disabled .................................................default
1
Enabled
6-5
FIFO Configuration Between the Two Channels
Primary Secondary
00
16
0
01
8
8......................................default
10
8
8
11
0
16
4
Reserved
........................................ always reads 1
3-2
Threshold for Primary Channel
00 1
01 3/4
10 1/2
.....................................................default
11 1/4
1-0
Threshold for Secondary Channel
00 1
01 3/4
10 1/2
.....................................................default
11 1/4
Offset 44 - Miscellaneous Control 1 ................................ RW
7
Reserved
........................................always reads 0
6
Master Read Cycle IRDY# Wait States
0
0 wait states
1
1 wait state.............................................default
5
Master Write Cycle IRDY# Wait States
0
0 wait states
1
1 wait state.............................................default
4
FIFO Output Data 1/2 Clock Advance
0
Disabled.................................................default
1
Enabled
3
Bus Master IDE Status Register Read Retry
Retry bus master IDE status register read when
master write operation for DMA read is not complete
0
Disabled
1
Enabled..................................................default
2
Reserved
........................................always reads 0
1
B-Channel Threshold Value 0 (3041 Silicon Only)
0
Disabled.................................................default
1
Enabled
0
A-Channel Threshold Value 0 (3041 Silicon Only)
0
Disabled.................................................default
1
Enabled
Offset 45 - Miscellaneous Control 2 ................................ RW
7
Reserved
........................................always reads 0
6
Interrupt Steering Swap
0
Don’t swap channel interrupts ...............default
1
Swap interrupts between the two channels
5-0
Reserved
........................................always reads 0
Offset 46 - Miscellaneous Control 3 ................................ RW
7
Primary Channel Read DMA FIFO Flush
1 = Enable FIFO flush for read DMA when interrupt
asserts primary channel. ...............default=1 (enabled)
6
Secondary Channel Read DMA FIFO Flush
1 = Enable FIFO flush for Read DMA when interrupt
asserts secondary channel............Default=1 (enabled)
5
Primary Channel End-of-Sector FIFO Flush
1 = Enable FIFO flush at the end of each sector for
the primary channel....................Default=0 (disabled)
4
Secondary Channel End-of-Sector FIFO Flush
1 = Enable FIFO flush at the end of each sector for
the secondary channel.................Default=0 (disabled)
3-2
Reserved
........................................always reads 0
1-0
Max DRDY Pulse Width
Maximum DRDY# pulse width after the cycle count.
Command will deassert in spite of DRDY# status to
avoid system ready hang.
00 No limitation..........................................default
01 64 PCI clocks
10 128 PCI clocks
11 192 PCI clocks
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