參數(shù)資料
型號： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁數(shù)： 17/95頁
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
Table 2.5. Interrupt Vector Assignments
Instruction Which
Can Cause
Exception
Return Address
Points to
Faulting
Instruction
Function
Interrupt
Number
Type
Divide Error
0
DIV, IDIV
Yes
FAULT
Debug Exception
1
Any Instruction
Yes
TRAP
*
NMI Interrupt
2
INT 2 or NMI
No
NMI
One-Byte Interrupt
3
INT
No
TRAP
Interrupt on Overflow
4
INTO
No
TRAP
Array Bounds Check
5
BOUND
Yes
FAULT
Invalid OP-Code
6
Any Illegal Instruction
Yes
FAULT
Device Not Available
7
ESC, WAIT
Yes
FAULT
Double Fault
8
Any Instruction That Can
Generate an Exception
ABORT
Coprocessor Segment Overrun
9
ESC
No
ABORT
Invalid TSS
10
JMP, CALL, IRET, INT
Yes
FAULT
Segment Not Present
11
Segment Register Instructions
Yes
FAULT
Stack Fault
12
Stack References
Yes
FAULT
General Protection Fault
13
Any Memory Reference
Yes
FAULT
Intel Reserved
14–15
D
D
D
Coprocessor Error
16
ESC, WAIT
Yes
FAULT
Intel Reserved
17–32
Two-Byte Interrupt
0–255
INT n
No
TRAP
*
Some debug exceptions may report both traps on the previous instruction, and faults on the next instruction.
Interrupts through Interrupt Gates automatically re-
set IF, disabling INTR requests. Interrupts through
Trap Gates leave the state of the IF bit unchanged.
Interrupts through a Task Gate change the IF bit ac-
cording to the image of the EFLAGs register in the
task’s Task State Segment (TSS). When an IRET
instruction is executed, the original state of the IF bit
is restored.
Non-Maskable Interrupt
Non-maskable interrupts provide a method of servic-
ing very high priority interrupts. When the NMI input
is pulled HIGH it causes an interrupt with an internal-
ly supplied vector value of 2. Unlike a normal hard-
ware interrupt no interrupt acknowledgement se-
quence is performed for an NMI.
While executing the NMI servicing procedure, the
80376 will not service any further NMI request, or
INT requests, until an interrupt return (IRET) instruc-
tion is executed or the processor is reset. If NMI
occurs while currently servicing an NMI, its presence
will be saved for servicing after executing the first
IRET instruction. The disabling of INTR requests de-
pends on the gate in IDT location 2.
Software Interrupts
A third type of interrupt/exception for the 80376 is
the software interrupt. An INT n instruction causes
the processor to execute the interrupt service rou-
tine pointed to by the n
th
vector in the interrupt table.
A special case of the two byte software interrupt
INT n is the one byte INT 3, or breakpoint interrupt.
By inserting this one byte instruction in a program,
the user can set breakpoints in his program as a
debugging tool.
17
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