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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 59/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
SOFTWARE TESTING FOR COPROCESSOR
PRESENCE
When
(80387SX) presence, it should use only the following
coprocessor
opcodes:
FNSTSW. To use other coprocessor opcodes when
a coprocessor is known to be not present, first set
EM
e
1 in the 80376 CR0 register.
software
is
used
to
test
coprocessor
FNINIT,
FNSTCW
and
5.0 PACKAGE THERMAL
SPECIFICATIONS
The Intel 80376 embedded processor is specified
for operation when case temperature is within the
range of 0
§
C–115
§
C for both the ceramic 88-pin
PGA package and the plastic 100-pin PQFP pack-
age. The case temperature may be measured in any
environment, to determine whether the 80376 is
within specified operating range. The case tempera-
ture should be measured at the center of the top
surface.
The ambient temperature is guaranteed as long as
T
c
is not violated. The ambient temperature can be
calculated from the
i
jc
and
i
ja
from the following
equations:
T
J
e
T
c
a
P
*
i
jc
T
A
e
T
j
b
P
*
i
ja
T
C
e
T
a
a
P
*[
i
ja
b
i
jc
]
Values for
i
ja
and
i
jc
are given in Table 5.1 for the
100-lead fine pitch.
i
ja
is given at various airflows.
Table 5.2 shows the maximum T
a
allowable (without
exceeding T
c
) at various airflows. Note that T
a
can
be improved further by attaching ‘‘fins’’ or a ‘‘heat
sink’’ to the package. P is calculated using the maxi-
mum
cold
I
cc
of 305 mA and the maximum V
CC
of
5.5V for both packages.
Table 5.1. 80376 Package Thermal
Characteristics Thermal Resistances
(
§
C/Watt)
i
jc
and
i
ja
i
ja
Versus Airflow-ft/min (m/sec)
Package
i
jc
0
200
400
600
800
1000
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
100-Lead 7.5 34.5 29.5
Fine Pitch
25.5
22.5
21.5
21.0
88-Pin
PGA
2.5 29.0 22.5
17.0
14.5
12.5
12.0
Table 5.2. 80376
Maximum Allowable Ambient
Temperature at Various Airflows
T
A
(
§
C) vs Airflow-ft/min (m/sec)
Package
i
jc
0
200
(0) (1.01) (2.03) (3.04) (4.06) (5.07)
400
600
800
1000
100-Lead 7.5 70
Fine Pitch
78
85
90
92
93
88-Pin
PGA
2.5 70
81
90
95
98
99
6.0 ELECTRICAL SPECIFICATIONS
The following sections describe recommended elec-
trical connections for the 80376, and its electrical
specifications.
6.1 Power and Grounding
The 80376 is implemented in CHMOS IV technology
and has modest power requirements. However, its
high clock frequency and 47 output buffers (address,
data, control, and HLDA) can cause power surges
as multiple output buffers drive new signal levels
simultaneously. For clean on-chip power distribution
at high frequency, 14 V
CC
and 18 V
SS
pins separate-
ly feed functional units of the 80376.
Power and ground connections must be made to all
external V
CC
and GND pins of the 80376. On the
circuit board, all V
CC
pins should be connected on a
V
CC
plane and all V
SS
pins should be connected on
a GND plane.
POWER DECOUPLING RECOMMENDATIONS
Liberal decoupling capacitors should be placed near
the 80376. The 80376 driving its 24-bit address bus
and 16-bit data bus at high frequencies can cause
transient power surges, particularly when driving
large capacitive loads. Low inductance capacitors
and interconnects are recommended for best high
frequency electrical performance. Inductance can
be reduced by shortening circuit board traces be-
tween the 80376 and decoupling capacitors as
much as possible.
RESISTOR RECOMMENDATIONS
The ERROR, FLT and BUSY inputs have internal
pull-up resistors of approximately 20 K
X
and the
PEREQ input has an internal pull-down resistor of
approximately 20 K
X
built into the 80376 to keep
these signals inactive when the 80387SX is not
present in the system (or temporarily removed from
its socket).
59
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