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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 72/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
than the calculated clock count due to instruction
sequences which execute faster than they can be
fetched from memory.
Instruction Clock Count Assumptions:
1. The instruction has been prefetched, decoded,
and is ready for execution.
2. Bus cycles do not require wait states.
3. There are no local bus HOLD requests delaying
processor acess to the bus.
4. No exceptions are detected during instruction ex-
ecution.
5. If an effective address is calculated, it does not
use two general register components. One regis-
ter, scaling and displacement can be used within
the clock counts showns. However, if the effec-
tive address calculation uses two general register
components, add 1 clock to the clock count
shown.
6. Memory reference instruction accesses byte or
aligned 16-bit operands.
Instruction Clock Count Notation
D If two clock counts are given, the smaller refers to
a register operand and the larger refers to a
memory operand.
Dn
e
number of times repeated.
Dm
e
number of components in the next instruc-
tion executed, where the entire displacement (if
any) counts as one component, the entire im-
mediate data (if any) counts as one component,
and all other bytes of the instruction and pre-
fix(es) each count as one component.
Misaligned or 32-Bit Operand Accesses:
D If instructions accesses a misaligned 16-bit oper-
and or 32-bit operand on even address add:
2
*
clocks for read or write.
4
**
clocks for read and write.
D If instructions accesses a 32-bit operand on odd
address add:
4
*
clocks for read or write.
8
**
clocks for read and write.
Wait States:
Wait states add 1 clock per wait state to instruction
execution for each data access.
72
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參數(shù)描述 |
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| 803763 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 1A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORM SNAP-IN INLET 1A |
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