- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378210 > 80376 (Intel Corp.) 32-BIT Embedded Microprocessor(32位嵌入式微處理器) PDF資料下載
參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 37/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁
376 EMBEDDED PROCESSOR
Wait states affect HOLD latency. The 80376 will not
honor a HOLD request until the end of the current
bus operation, no matter how many wait states are
required. Systems with DMA where data transfer is
critical must insure that READY returns sufficiently
soon.
COPROCESSOR INTERFACE SIGNALS
(PEREQ, BUSY, ERROR)
In the following sections are descriptions of signals
dedicated to the numeric coprocessor interface. In
addition to the data bus, address bus, and bus cycle
definition signals, these following signals control
communication
between
80387SX processor extension.
the
80376
and
the
Coprocessor Request (PEREQ)
When asserted (HIGH), this input signal indicates a
coprocessor request for a data operand to be trans-
ferred to/from memory by the 80376. In response,
the 80376 transfers information between the co-
processor and memory. Because the 80376 has in-
ternally stored the coprocessor opcode being exe-
cuted, it performs the requested data transfer with
the correct direction and memory address.
PEREQ is a level-sensitive active HIGH asynchro-
nous signal. Setup and hold times, t
29
and t
30
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This signal is
provided with a weak internal pull-down resistor of
around 20 K
X
to ground so that it will not float active
when left unconnected.
Coprocessor Busy (BUSY)
When asserted (LOW), this input indicates the co-
processor is still executing an instruction, and is not
yet able to accept another. When the 80376 en-
counters any coprocessor instruction which oper-
ates on the numerics stack (e.g. load, pop, or arith-
metic operation), or the WAIT instruction, this input
is first automatically sampled until it is seen to be
inactive. This sampling of the BUSY input prevents
overrunning the execution of a previous coprocessor
instruction.
The F(N)INIT, F(N)CLEX coprocessor instructions
are allowed to execute even if BUSY is active, since
these instructions are used for coprocessor initializa-
tion and exception-clearing.
BUSY is an active LOW, level-sensitive asynchro-
nous signal. Setup and hold times, t
29
and t
30
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 K
X
to V
CC
so that it will not float active when left
unconnected.
BUSY serves an additional function. If BUSY is sam-
pled LOW at the falling edge of RESET, the 80376
processor performs an internal self-test (see
Bus
Activity During and Following Reset.
If BUSY is
sampled HIGH, no self-test is performed.
Coprocessor Error (ERROR)
When asserted (LOW), this input signal indicates
that the previous coprocessor instruction generated
a coprocessor error of a type not masked by the
coprocessor’s control register. This input is automat-
ically sampled by the 80376 when a coprocessor
instruction is encountered, and if active, the 80376
generates exception 16 to access the error-handling
software.
Several coprocessor instructions, generally those
which clear the numeric error flags in the coproces-
sor or save coprocessor state, do execute without
the
80376
generating
ERROR is active. These instructions are FNINIT,
FNCLEX,
FNSTSW,
FNSTSWAX,
FNSTENV and FNSAVE.
exception
16
even
if
FNSTCW,
ERROR is an active LOW, level-sensitive asynchro-
nous signal. Setup and hold times t
29
and t
30
, rela-
tive to the CLK2 signal must be met to guarantee
recognition at a particular clock edge. This pin is pro-
vided with a weak internal pull-up resistor of around
20 K
X
to V
CC
so that it will not float active when left
unconnected.
37
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 804-2 | RECTIFIERS ASSEMBLIES |
| 804-3 | RECTIFIERS ASSEMBLIES |
| 804-4 | RECTIFIERS ASSEMBLIES |
| 8040AHL | HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER |
| 8048AH | HMOS SINGLE-COMPONENT 8-BIT MICROCONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 803760 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 3A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORMANCE IEC INLET 3A |
| 803761 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 6A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORMANCE IEC INLET 6A |
| 803762 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 10A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORMANCE IEC INLET 10A |
| 803763 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 1A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORM SNAP-IN INLET 1A |
| 803764 | 制造商:Schaffner 功能描述:Power Entry Module Filtered M 3 POS 250VAC 3A ST 1 Port 制造商:Schaffner 功能描述:FILTER PERFORM SNAP-IN INLET 3A |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。