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參數(shù)資料
| 型號(hào)： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁(yè)數(shù)： | 27/95頁(yè) |
| 文件大小： | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
31
16
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE
31 . . . 24
G 0 0 0
LIMIT
19 . . . 16
P
DPL
0
TYPE
BASE
23 . . . 16
a
4
Type
0
1
2
3
4
5
6
7
Defines
Invalid
Reserved
LDT
Reserved
Reserved
Task Gate (80376/80386 Task)
Reserved
Reserved
Type
8
9
A
B
C
D
E
F
Defines
Invalid
Available 80376/80386 TSS
Undefined (Intel Reserved)
Busy 80376/80386 TSS
80376/80386 Call Gate
Undefined (Intel Reserved)
80376/80386 Interrupt Gate
80376/80386 Trap Gate
Figure 3.5. System Descriptors
240182–13
Figure 3.6. Example Descriptor Selection
3.3 Protection
The 80376 offers extensive protection features.
These protection features are particularly useful in
sophisticated embedded applications which use
multitasking real-time operating systems. For sim-
pler embedded applications these protection capa-
bilities can be easily bypassed by making all applica-
tions run at privilege level (PL) 0.
RULES OF PRIVILEGE
The 80376 controls access to both data and proce-
dures between levels of a task, according to the fol-
lowing rules.
DData stored in a segment with privilege level
p
can be accessed only by code executing at a
privilege level at least as privileged as
p.
DA code segment/procedure with privilege level
p
can only be called by a task executing at the
same or a lesser privilege level than
p.
PRIVILEGE LEVELS
At any point in time, a task on the 80376 always
executes at one of the four privilege levels. The Cur-
rent Privilege Level (CPL) specifies what the task’s
privilege level is. A task’s CPL may only be changed
27
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