參數(shù)資料
型號： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁數(shù)： 78/95頁
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
Table 8.1. 80376 Instruction Set Clock Count Summary
(Continued)
Clock
Counts
Number
of Data
Cycles
Instruction
Format
Notes
REPEATED STRING MANIPULATION
(Continued)
REPNE CMPS
e
Compare String
(Find Match)
1 1 1 1 0 0 1 0
1 0 1 0 0 1 1 w
5
a
9n
**
7
a
6n
*
2n
**
1n
*
a
REP INS
e
Input String
1 1 1 1 0 0 1 1
0 1 1 0 1 1 0 w
27
a
6n
*
5
a
6n
*
1n
*
1n
*
a,f,k
a,f,l
REP LODS
e
Load String
1 1 1 1 0 0 1 1
1 0 1 0 1 1 0 w
a
REP MOVS
e
Move String
1 1 1 1 0 0 1 1
1 0 1 0 0 1 0 w
7
a
4n
**
6
a
5n
*
2n
**
1n
*
1n
*
a
REP OUTS
e
Output String
1 1 1 1 0 0 1 1
0 1 1 0 1 1 1 w
26
a
5n
*
a,f,k
a,f,l
REPE SCAS
e
Scan String
(Find Non-AL/AX/EAX)
1 1 1 1 0 0 1 1
1 0 1 0 1 1 1 w
5
a
8n
*
1n
*
a
REPNE SCAS
e
Scan String
(Find AL/AX/EAX)
1 1 1 1 0 0 1 0
1 0 1 0 1 1 1 w
5
a
8n
*
1n
*
a
REP STOS
e
Store String
1 1 1 1 0 0 1 1
1 0 1 0 1 0 1 w
5
a
5n
*
1n
*
a
BIT MANIPULATION
BSF
e
Scan Bit Forward
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 0
mod reg
r/m
10
a
3n
**
2n
**
a
BSR
e
Scan Bit Reverse
0 0 0 0 1 1 1 1
1 0 1 1 1 1 0 1
mod reg
r/m
10
a
3n
**
2n
**
a
BT
e
Test Bit
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0
mod 1 0 0
r/m immed 8-bit data
3/6
*
0/1
*
a
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 0 0 1 1
mod reg
r/m
3/12
*
0/1
*
a
BTC
e
Test Bit and Complement
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0
mod 1 1 1
r/m immed 8-bit data
6/8
*
0/2
*
a
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 1
mod reg
r/m
6/13
*
0/2
*
a
BTR
e
Test Bit and Reset
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0
mod 1 1 0
r/m immed 8-bit data
6/8
*
0/2
*
a
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 1 0 0 1 1
mod reg
r/m
6/13
*
0/2
*
a
BTS
e
Test Bit and Set
Register/Memory, Immediate
0 0 0 0 1 1 1 1
1 0 1 1 1 0 1 0
mod 1 0 1
r/m immed 8-bit data
6/8
*
0/2
*
a
Register/Memory, Register
0 0 0 0 1 1 1 1
1 0 1 0 1 0 1 1
mod reg
r/m
6/13
*
0/2
*
a
CONTROL TRANSFER
CALL
e
Call
Direct within Segment
1 1 1 0 1 0 0 0
full displacement
9
a
m
*
2
j
Register/Memory
Indirect within Segment
1 1 1 1 1 1 1 1
mod 0 1 0
r/m
9
a
m/12
a
m
2/3
a, j
Direct Intersegment
1 0 0 1 1 0 1 0
unsigned full offset, selector
42
a
m
9
c, d, j
78
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