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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 18/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
A final type of software interrupt, is the single step
interrupt. It is discussed in
Single-Step Trap
(page
22).
INTERRUPT AND EXCEPTION PRIORITIES
Interrupts are externally-generated events. Maska-
ble Interrupts (on the INTR input) and Non-Maskable
Interrupts (on the NMI input) are recognized at in-
struction boundaries. When NMI and maskable
INTR are
both
recognized at the
same
instruction
boundary, the 80376 invokes the NMI service rou-
tine first. If, after the NMI service routine has been
invoked, maskable interrupts are still enabled, then
the 80376 will invoke the appropriate interrupt serv-
ice routine.
As the 80376 executes instructions, it follows a con-
sistent cycle in checking for exceptions, as shown in
Table 2.6. This cycle is repeated as each instruction
is executed, and occurs in parallel with instruction
decoding and execution.
INSTRUCTION RESTART
The 80376 fully supports restarting all instructions
after faults. If an exception is detected in the instruc-
tion to be executed (exception categories 4 through
9 in Table 2.6), the 80376 device invokes the appro-
priate exception service routine. The 80376 is in a
state that permits restart of the instruction.
DOUBLE FAULT
A Double fault (exception 8) results when the proc-
essor attempts to invoke an exception service rou-
tine for the segment exceptions (10, 11, 12 or 13),
but in the process of doing so, detects an exception.
2.8 Reset and Initialization
When the processor is Reset the registers have the
values shown in Table 2.7. The 80376 will then start
executing instructions near the top of physical mem-
ory, at location 0FFFFF0H. A short JMP should be
executed within the segment defined for power-up
(see Table 2.7). The GDT should then be initialized
for a start-up data and code segment followed by a
far JMP that will load the segment descriptor cache
with the new descriptor values. The IDT table, after
reset, is located at physical address 0H, with a limit
of 256 entries.
RESET forces the 80376 to terminate all execution
and local bus activity. No instruction execution or
bus activity will occur as long as Reset is active.
Between 350 and 450 CLK2 periods after Reset be-
comes inactive, the 80376 will start executing in-
structions at the top of physical memory.
Table 2.6. Sequence of Exception Checking
Consider the case of the 80376 having just completed an instruction. It then performs the following checks
before reaching the point where the next instruction is completed:
1. Check for Exception 1 Traps from the instruction just completed (single-step via Trap Flag, or Data
Breakpoints set in the Debug Registers).
2. Check for external NMI and INTR.
3. Check for Exception 1 Faults in the next instruction (Instruction Execution Breakpoint set in the
Debug Registers for the next instruction).
4. Check for Segmentation Faults that prevented fetching the entire next instruction (exceptions 11 or
13).
5. Check for Faults decoding the next instruction (exception 6 if illegal opcode; or exception 13 if
instruction is longer than 15 bytes, or privilege violation (i.e. not at IOPL or at CPL
e
0).
6. If WAIT opcode, check if TS
e
1 and MP
e
1 (exception 7 if both are 1).
7. If ESCape opcode for numeric coprocessor, check if EM
e
1 or TS
e
1 (exception 7 if either are 1).
8. If WAIT opcode or ESCape opcode for numeric coprocessor, check ERROR input signal (exception
16 if ERROR input is asserted).
9. Check for Segmentation Faults that prevent transferring the entire memory quantity (exceptions 11,
12, 13).
18
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