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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 42/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
240182–20
Figure 4.5. Fastest Read Cycles with Pipelined Timing
READ AND WRITE CYCLES
Data transfers occur as a result of bus cycles, classi-
fied as read or write cycles. During read cycles, data
is transferred from an external device to the proces-
sor. During write cycles, data is transferred from the
processor to an external device.
Two choices of bus cycle timing are dynamically se-
lectable: non-pipelined or pipelined. After an idle bus
state, the processor always uses non-pipelined tim-
ing. However the NA (Next Address) input may be
asserted to select pipelined timing for the next bus
cycle. When pipelining is selected and the 80376
has a bus request pending internally, the address
and definition of the next cycle is made available
even before the current bus cycle is acknowledged
by READY.
Terminating a read or write cycle, like any bus cycle,
requires acknowledging the cycle by asserting the
READY input. Until acknowledged, the processor in-
serts wait states into the bus cycle, to allow adjust-
ment for the speed of any external device. External
hardware, which has decoded the address and bus
cycle type, asserts the READY input at the appropri-
ate time.
At the end of the second bus state within the bus
cycle, READY is sampled. At that time, if external
hardware acknowledges the bus cycle by asserting
READY, the bus cycle terminates as shown in Figure
4.6. If READY is negated as in Figure 4.7, the 80376
executes another bus state (a wait state) and
READY is sampled again at the end of that state.
This continues indefinitely until the cycle is acknowl-
edged by READY asserted.
When the current cycle is acknowledged, the 80376
terminates it. When a read cycle is acknowledged,
the 80376 latches the information present at its data
pins. When a write cycle is acknowledged, the write
data of the 80376 remains valid throughout phase
one of the next bus state, to provide write data hold
time.
42
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