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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 45/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
240182–23
Bus States:
T1Dfirst clock of a non-pipelined bus cycle (80376 drives new address and asserts ADS).
T2Dsubsequent clocks of a bus cycle when NA has not been sampled asserted in the current bus cycle.
TiDidle state.
ThDhold acknowledge state (80376 asserts HLDA).
The fastest bus cycle consists of two states: T1 and T2.
Four basic bus states describe bus operation when not using pipelined address.
Figure 4.8. 80376 Bus States (Not Using Pipelined Address)
Bus cycles always begin with T1. T1 always leads to
T2. If a bus cycle is not acknowledged during T2 and
NA is inactive, T2 is repeated. When a cycle is ac-
knowledged during T2, the following state will be T1
of the next bus cycle if a bus request is pending
internally, or T
i
if there is no bus request pending, or
T
h
if the HOLD input is being asserted.
Use of pipelining allows the 80376 to enter three
additional bus states not shown in Figure 4.8. Figure
4.12 is the complete bus state diagram, including
pipelined cycles.
Pipelined Bus Cycles
Pipelining is the option of requesting the address
and the bus cycle definition of the next inter-
nally pending bus cycle before the current bus cycle
is acknowledged with READY asserted. ADS is as-
serted by the 80376 when the next address is is-
sued. The pipelining option is controlled on a cycle-
by-cycle basis with the NA input signal.
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state, the NA input is sampled at the end of every
phase one until the bus cycle is acknowledged. Dur-
ing non-pipelined bus cycles NA is sampled at the
end of phase one in every T2. An example is Cycle 2
in Figure 4.9, during which NA is sampled at the end
of phase one of every T2 (it was asserted once dur-
ing the first T2 and has no further effect during that
bus cycle).
45
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