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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 55/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
240182–32
NOTE:
HOLD is a synchronous input and can be asserted at any CLK2 edge, provided setup and hold (t
23
and t
24
) require-
ments are met. This waveform is useful for determining Hold Acknowledge latency.
Figure 4.17. Requesting Hold from Active Bus (NA Inactive)
guaranteed to enter FLOAT in a valid state. After
deactivating FLT, the 80376 is not guaranteed to
exit FLOAT mode in a valid state. This is not a prob-
lem as the FLT pin is meant to be used only during
ONCE. After exiting FLOAT, the 80376 must be re-
set to return it to a valid state. Reset should be as-
serted before FLT is deasserted. This will ensure
that the 80376 will exit float in a valid state.
FLT has an internal pull-up resistor, and if it is not
used it should be unconnected.
BUS ACTIVITY DURING AND FOLLOWING
RESET
RESET is the highest priority input signal, capable of
interrupting any processor activity when it is assert-
ed. A bus cycle in progress can be aborted at any
stage, or idle states or bus hold acknowledge states
discontinued so that the reset state is established.
RESET should remain asserted for at least 15 CLK2
periods to ensure it is recognized throughout the
80376, and at least 80 CLK2 periods if a 80376 self-
test is going to be requested at the falling edge. RE-
SET asserted pulses less than 15 CLK2 periods may
not be recognized. RESET pulses less than 80 CLK2
periods followed by a self-test may cause the self-
test to report a failure when no true failure exists.
Provided the RESET falling edge meets setup and
hold times t
25
and t
26
, the internal processor clock
phase is defined at that time as illustrated by Figure
4.19 and Figure 6.7.
55
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