參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 44/95頁(yè)
文件大小： 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
240182–22
Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 4.7. Various Non-Pipelined Bus Cycles (Various Number of Wait States)
Figure 4.7 illustrates non-pipelined bus cycles with
one wait state added to Cycles 2 and 3. READY is
sampled inactive at the end of the first T2 in Cycles
2 and 3. Therefore Cycles 2 and 3 have T2 repeated
again. At the end of the second T2, READY is sam-
pled active.
When address pipelining is not used, the address
and bus cycle definition remain valid during all wait
states. When wait states are added and it is desir-
able to maintain non-pipelined timing, it is necessary
to negate NA during each T2 state except the
last one, as shown in Figure 4.7, Cycles 2 and 3. If
NA is sampled active during a T2 other than the last
one, the next state would be T2I or T2P instead of
another T2.
When address pipelining is not used, the bus states
and transitions are completely illustrated by Figure
4.8. The bus transitions between four possible
states, T1, T2, T
i
, and T
h
. Bus cycles consist of T1
and T2, with T2 being repeated for wait states. Oth-
erwise the bus may be idle, T
i
, or in the hold ac-
knowledge state T
h
.
44
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