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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 25/95頁 |
| 文件大小： | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
vides both isolation and protection for a task’s seg-
ments, while still allowing global data to be shared
among tasks.
Unlike the 6-byte GDT or IDT registers which contain
a base address and limit, the visible portion of the
LDT register contains only a 16-bit selector. This se-
lector refers to a Local Descriptor Table descriptor in
the GDT (see Figure 2.1).
INTERRUPT DESCRIPTOR TABLE
The third table needed for 80376 systems is the In-
terrupt Descriptor Table. The IDT contains the de-
scriptors which point to the location of up to 256
interrupt service routines. The IDT may contain only
task gates, interrupt gates and trap gates. The IDT
should be at least 256 bytes in size in order to hold
the descriptors for the 32 Intel Reserved Interrupts.
Every interrupt used by a system must have an entry
in the IDT. The IDT entries are referenced by INT
instructions, external interrupt vectors, and excep-
tions.
DESCRIPTORS
The object to which the segment selector points to
is called a descriptor. Descriptors are eight-byte
quantities which contain attributes about a given
region of linear address space. These attributes in-
clude the 32-bit logical base address of the seg-
ment, the 20-bit length and granularity of the seg-
ment, the protection level, read, write or execute
privileges, and the type of segment. All of the attri-
bute information about a segment is contained in 12
bits in the segment descriptor. Figure 3.3 shows the
general format of a descriptor. All segments on the
the 80376 have three attribute fields in common: the
Present bit (P), the Descriptor Privilege Level bits
(DPL) and the Segment bit (S). P
e
1 if the segment
is loaded in physical memory, if P
e
0 then any
attempt to access the segment causes a not present
exception (exception 11). The DPL is a two-bit field
which specifies the protection level, 0–3, associated
with a segment.
The 80376 has two main categories of segments:
system segments, and non-system segments (for
code and data). The segment bit, S, determines if a
given segment is a system segment, a code seg-
ment or a data segment. If the S bit is 1 then the
segment is either a code or data segment, if it is 0
then the segment is a system segment.
Note that although the 80376 is limited to a
16-Mbyte Physical address space (2
24
), its base ad-
dress allows a segment to be placed anywhere in a
4-Gbyte linear address space. When writing code for
the 80376, users should keep code portability to an
80386 processor (or other processors with a larger
physical address space) in mind. A segment base
address can be placed anywhere in this 4-Gbyte lin-
ear address space, but a physical address will be
31
0
BYTE
ADDRESS
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
3BASE
A
LIMIT
BASE
23 . . . 16
a
4
P
DPL
S
TYPE
A
L
BASE
LIMIT
P
DPL
S
TYPE
A
G
Base Address of the segment
The length of the segment
Present Bit
1
e
Present
Descriptor Privilege Level 0–3
Segment Descriptor:
Type of Segment
Accessed Bit
Granularity Bit
0
e
Not Present
0
e
System Descriptor,
1
e
Code or Data Descriptor
1
e
Segment length is 4 Kbyte Granular
0
e
Segment length is byte granular
Bit must be zero (0) for compatibility with future processors
Available field for user or OS
0
AVL
Figure 3.3. Segment Descriptors
31
0
SEGMENT BASE 15 . . . 0
SEGMENT LIMIT 15 . . . 0
0
BASE
31 . . . 24
A
LIMIT
19 . . . 16
ACCESS
RIGHTS
BYTE
BASE
23 . . . 16
G 1 0 V
a
4
L
G
Granularity Bit
1
e
Segment length is 4 Kbyte granular
0
e
Segment length is byte granular
Bit must be zero (0) for compatibility with future processors
AVL Available field for user or OS
0
Figure 3.4. Code and Data Descriptors
25
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