參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 36/95頁(yè)
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
READY is ignored on the first bus state of all bus
cycles, and sampled each bus state thereafter until
asserted. READY must eventually be asserted to ac-
knowledge every bus cycle, including Halt Indication
and Shutdown Indication bus cycles. When being
sampled, READY must always meet setup and hold
times t
19
and t
20
for correct operation.
Next Address Request (NA)
This is used to request pipelining. This input indi-
cates the system is prepared to accept new values
of BHE, BLE, A
23
–A
1
, W/R, D/C and M/IO from the
80376 even if the end of the current cycle is not
being acknowledged on READY. If this input is ac-
tive when sampled, the next bus cycle’s address and
status signals are driven onto the bus, provided the
next bus request is already pending internally. NA is
ignored in clock cycles in which ADS or READY is
activated. This signal is active LOW and must satisfy
setup and hold times t
15
and t
16
for correct opera-
tion. See
Pipelined Bus Cycles
and
Read and
Write Cycles
for additional information.
BUS ARBITRATION SIGNALS (HOLD, HLDA)
This section describes the mechanism by which the
processor relinquishes control of its local buses
when requested by another bus master device. See
Entering and Exiting Hold Acknowledge
for addi-
tional information.
Bus Hold Request (HOLD)
This input indicates some device other than the
80376 requires bus mastership. When control is
granted, the 80376 floats A
23
–A
1
, BHE, BLE,
D
15
–D
0
, LOCK, M/IO, D/C, W/R and ADS, and
then activates HLDA, thus entering the bus hold ac-
knowledge state. The local bus will remain granted
to the requesting master until HOLD becomes inac-
tive. When HOLD becomes inactive, the 80376 will
deactivate HLDA and drive the local bus (at the
same time), thus terminating the hold acknowledge
condition.
HOLD must remain asserted as long as any other
device is a local bus master. External pull-up resis-
tors may be required when in the hold acknowledge
state since none of the 80376 floated outputs have
internal pull-up resistors. See
Resistor Recommen-
dations
for additional information. HOLD is not rec-
ognized while RESET is active but is recognized dur-
ing the time between the high-to-low transistion of
RESET and the first instruction fetch. If RESET is
asserted while HOLD is asserted, RESET has priori-
ty and places the bus into an idle state, rather than
the hold acknowledge (high-impedance) state.
HOLD is a level-sensitive, active HIGH, synchronous
input. HOLD signals must always meet setup and
hold times t
23
and t
24
for correct operation.
Bus Hold Acknowledge (HLDA)
When active (HIGH), this output indicates the 80376
has relinquished control of its local bus in response
to an asserted HOLD signal, and is in the bus Hold
Acknowledge state.
The Bus Hold Acknowledge state offers near-com-
plete signal isolation. In the Hold Acknowledge
state, HLDA is the only signal being driven by the
80376. The other output signals or bidirectional sig-
nals (D
15
–D
0
, BHE, BLE, A
23
–A
1
, W/R, D/C, M/IO,
LOCK and ADS) are in a high-impedance state so
the requesting bus master may control them. These
pins remain OFF throughout the time that HLDA re-
mains active (see Table 4.3). Pull-up resistors may
be desired on several signals to avoid spurious ac-
tivity when no bus master is driving them. See
Re-
sistor Recommendations
for additional informa-
tion.
When the HOLD signal is made inactive, the 80376
will deactivate HLDA and drive the bus. One rising
edge on the NMI input is remembered for processing
after the HOLD input is negated.
Table 4.3. Output Pin State during HOLD
Pin Value
Pin Names
1
Float
HLDA
LOCK, M/IO, D/C, W/R,
ADS, A
23
–A
1
, BHE, BLE,
D
15
–D
0
Hold Latencies
The maximum possible HOLD latency depends on
the software being executed. The actual HOLD la-
tency at any time depends on the current bus activi-
ty, the state of the LOCK signal (internal to the CPU)
activated by the LOCK prefix, and interrupts. The
80376 will not honor a HOLD request until the cur-
rent bus operation is complete.
The 80376 breaks 32-bit data or I/O accesses into 2
internally locked 16-bit bus cycles; the LOCK signal
is not asserted. The 80376 breaks unaligned 16-bit
or 32-bit data or I/O accesses into 2 or 3 internally
locked 16-bit bus cycles. Again the LOCK signal is
not asserted but a HOLD request will not be recog-
nized until the end of the entire transfer.
36
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