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參數(shù)資料
| 型號： | 80376 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-BIT Embedded Microprocessor(32位嵌入式微處理器) |
| 中文描述： | 32位嵌入式微處理器（32位嵌入式微處理器） |
| 文件頁數(shù)： | 22/95頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | 80376 |
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376 EMBEDDED PROCESSOR
2.10 Self-Test
The 80376 has the capability to perform a self-test.
The self-test checks the function of all of the Control
ROM and most of the non-random logic of the part.
Approximately one-half of the 80376 can be tested
during self-test.
Self-Test is initiated on the 80376 when the RESET
pin transitions from HIGH to LOW, and the BUSY pin
is LOW. The self-test takes about 2
20
clocks, or ap-
proximately 33 ms with a 16 MHz 80376 processor.
At the completion of self-test the processor per-
forms reset and begins normal operation. The part
has successfully passed self-test if the contents of
the EAX register is zero. If the EAX register is not
zero then the self-test has detected a flaw in the
part. If self-test is not selected after reset, EAX may
be non-zero after reset.
2.11 Debugging Support
The 80376 provides several features which simplify
the debugging process. The three categories of on-
chip debugging aids are:
1. The code execution breakpoint opcode (0CCH).
2. The single-step capability provided by the TF bit
in the flag register, and
3. The code and data breakpoint capability provided
by the Debug Registers DR0–3, DR6, and DR7.
BREAKPOINT INSTRUCTION
A single-byte software interrupt (Int 3) breakpoint in-
struction is available for use by software debuggers.
The breakpoint opcode is 0CCh, and generates an
exception 3 trap when executed.
DEBUG REGISTERS
240182–9
240182–10
240182–5
Figure 2.6. Debug Registers
22
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