參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 9/95頁(yè)
文件大小： 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
Table 2.1. Flag Definitions
Bit Position
0
2
Name
CF
PF
Function
Carry Flag
DSet on high-order bit carry or borrow; cleared otherwise.
Parity Flag
DSet if low-order 8 bits of result contain an even number
of 1-bits; cleared otherwise.
Auxiliary Carry Flag
DSet on carry from or borrow to the low order
four bits of AL; cleared otherwise.
Zero Flag
DSet if result is zero; cleared otherwise.
Sign Flag
DSet equal to high-order bit of result (0 if positive, 1 if
negative).
Single Step Flag
DOnce set, a single step interrupt occurs after the
next instruction executes. TF is cleared by the single step interrupt.
Interrupt-Enable Flag
DWhen set, external interrupts signaled on the
INTR pin will cause the CPU to transfer control to an interrupt vector
specified location.
Direction Flag
DCauses string instructions to auto-increment (default)
the appropriate index registers when cleared. Setting DF causes auto-
decrement.
Overflow Flag
DSet if the operation resulted in a carry/borrow into
the sign bit (high-order bit) of the result but did not result in a
carry/borrow out of the high-order bit or vice-versa.
I/O Privilege Level
DIndicates the maximum CPL permitted to
execute I/O instructions without generating an exception 13 fault or
consulting the I/O permission bit map. It also indicates the maximum
CPL value allowing alteration of the IF bit.
Nested Task
DIndicates that the execution of the current task is
nested within another task (see
Task Switching
).
Resume Flag
DUsed in conjunction with debug register breakpoints. It
is checked at instruction boundaries before breakpoint processing. If
set, any debug fault is ignored on the next instruction. It is reset at the
successful completion of any instruction except IRET, POPF, and
those instructions causing task switches.
4
AF
6
7
ZF
SF
8
TF
9
IF
10
DF
11
OF
12, 13
IOPL
14
NT
16
RF
CONTROL REGISTER
The 80376 has a 32-bit control register called CR0 that is used to control coprocessor emulation. This register
is shown in Figures, 2.1 and 2.2. The defined CR0 bits are described in Table 2.2. Bits 0, 4 and 31 of CR0 have
fixed values in the 80376. These values cannot be changed. Programs that load CR0 should always load bits
0, 4 and 31 with values previously there to be compatible with the 80386.
Table 2.2. CR0 Definitions
Bit Position
1
Name
MP
Function
Monitor Coprocessor Extension
DAllows WAIT instructions to cause
a processor extension not present exception (number 7).
Emulate Processor Extension
DWhen set, this bit causes a
processor extension not present exception (number 7) on ESC
instructions to allow processor extension emulation.
Task Switched
DWhen set, this bit indicates the next instruction using
a processor extension will cause exception 7, allowing software to test
whether the current processor extension context belongs to the
current task (see
Task Switching
).
2
EM
3
TS
9
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