參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 43/95頁(yè)
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
240182–21
Idle states are shown here for diagram variety only. Write cycles are not always followed by an idle state. An active bus
cycle can immediately follow the write cycle.
Figure 4.6. Various Non-Pipelined Bus Cycles (Zero Wait States)
Non-Pipelined Bus Cycles
Any bus cycle may be performed with non-pipelined
timing. For example, Figure 4.6 shows a mixture of
non-pipelined read and write cycles. Figure 4.6
shows that the fastest possible non-pipelined cycles
have two bus states per bus cycle. The states are
named T1 and T2. In phase one of T1, the address
signals and bus cycle definition signals are driven
valid and, to signal their availability, address strobe
(ADS) is simultaneously asserted.
During read or write cycles, the data bus behaves as
follows. If the cycle is a read, the 80376 floats its
data signals to allow driving by the external device
being addressed.
The 80376 requires that all data
bus pins be at a valid logic state (HIGH or LOW)
at the end of each read cycle, when READY is
asserted. The system MUST be designed to
meet this requirement.
If the cycle is a write, data
signals are driven by the 80376 beginning in phase
two of T1 until phase one of the bus state following
cycle acknowledgement.
43
相關(guān)PDF資料
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804-2 RECTIFIERS ASSEMBLIES
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804-4 RECTIFIERS ASSEMBLIES
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