參數(shù)資料
型號(hào)： 80376
廠商： Intel Corp.
英文描述： 32-BIT Embedded Microprocessor(32位嵌入式微處理器)
中文描述： 32位嵌入式微處理器（32位嵌入式微處理器）
文件頁(yè)數(shù)： 33/95頁(yè)
文件大?。?/td> 1086K
代理商： 80376
376 EMBEDDED PROCESSOR
starting the pending bus cycle before the present
bus cycle is finished. A non-pipelined bus cycle
gives the highest bus performance by executing ev-
ery bus cycle in two processor clock cycles. For
maximum design flexibility, the address pipelining
option is selectable on a cycle-by-cycle basis.
The processor’s bus cycle is the basic mechanism
for information transfer, either from system to proc-
essor, or from processor to system. 80376 bus cy-
cles perform data transfer in a minimum of only two
clock periods. On a 16-bit data bus, the maximum
80376 transfer bandwidth at 16 MHz is therefore
16 Mbytes/sec. However, any bus cycle will be ex-
tended for more than two clock periods if external
hardware withholds acknowledgement of the cycle.
The 80376 can relinquish control of its local buses
to allow mastership by other devices, such as direct
memory
access
(DMA)
quished, HLDA is the only output pin driven by the
80376, providing near-complete isolation of the
channels.
When
relin-
processor from its system (all other output pins are
in a float condition).
4.1 Signal Description Overview
Ahead is a brief description of the 80376 input and
output signals arranged by functional groups.
The signal descriptions sometimes refer to A.C. tim-
ing parameters, such as ‘‘t
25
Reset Setup Time’’ and
‘‘t
26
Reset Hold Time.’’ The values of these parame-
ters can be found in Tables 6.4 and 6.5.
CLOCK (CLK2)
CLK2 provides the fundamental timing for the
80376. It is divided by two internally to generate the
internal processor clock used for instruction execu-
tion. The internal clock is comprised of two
240182–17
Figure 4.2. CLK2 Signal and Internal Processor Clock
33
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