參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 101/104頁(yè)
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤(pán)
AD9547
Data Sheet
Rev. E | Page 96 of 104
Table 146. Save
Address
Bit
Bit Name
Description
0x0E02
[7:1]
Unused
Unused.
0
Save to EEPROM
Upload data to the EEPROM based on in the EEPROM storage sequence. This is an autoclearing bit.
When an EEPROM save/load transfer is complete, wait a minimum of 10 μs before starting the next
EEPROM save/load transfer.
Table 147. Load
Address
Bit
Bit Name
Description
0x0E03
[7:2]
Unused
Unused.
1
Loadfrom
EEPROM
Download data from the EEPROM. This is an autoclearing bit. Whenan EEPROM save/load transfer is
complete, wait a minimum of 10 μs before starting the next EEPROM save/load transfer.
0
Unused
Unused.
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F)
The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. The following is a description
of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage sequence.
Table 148. EEPROM Storage Sequencefor System Clock Settings
Address
Bit
Bit Name
Description
0x0E10
[7:0]
System clock
The default value of this register is 0x08, which the controller interprets as a data instruction. Its
decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the
address specifiedby the next two bytes. The controller stores 0x08 in the EEPROM and increments
the EEPROM address pointer.
0x0E11
[7:0]
System clock
The default value of these two registers is 0x0100. Note that Register 0x0E11 and Register 0x0E12 are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0100). The controller stores 0x0100 inthe EEPROM and incrementsthe EEPROM pointer by 2.
It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and
increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine
bytes transferred correspond to the system clock parameters inthe register map.
0x0E12
[7:0]
0x0E13
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update instruction.
The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Table 149. EEPROM Storage Sequencefor System Clock Calibration
Address
Bit
Bit Name
Description
0x0E14
[7:0]
SYSCLK calibrate
The default value of this register is 0xA0, which the controller interprets as a calibrate instruction.
The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.
Table 150. EEPROM Storage Sequencefor General Configuration Settings
Address
Bit
Bit Name
Description
0x0E15
[7:0]
General
The default value of this register is 0x14, which the controller interprets as a data instruction. Its
decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the
address specifiedby the next two bytes. The controller stores 0x14 in the EEPROM and increments
the EEPROM address pointer.
0x0E16
[7:0]
General
The default value of these two registers is 0x0200. Note that Register
0x0E16 and Register 0x0E17 are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a startingaddress (inthis case,
0x0200). The controller stores 0x0200inthe EEPROM and increments the EEPROM pointer by 2. It then
transfers 21 bytes from the register map (beginning at Address 0x0200) to the EEPROM and incre-
ments the EEPROM address pointer by 22 (21 data bytes and one checksum byte). The 21 bytes
transferred correspond to the general configuration parameters inthe register map.
0x0E17
[7:0]
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