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| 型號(hào)： | AD9547BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9547 Mask Change 20/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9547
Data Sheet
Rev. E | Page 26 of 104
THEORY OF OPERATION
TW CLAMP
AND
HISTORY
PROG.
DIGITAL
LOOP
FILTER
TDC/PFD
÷R
÷S
DIGITAL PLL CORE
HOLDOVER
LOGIC
CONTROL
LOGIC
LOW NOISE
CLOCK
MULTIPLIER
AMP
SYSCLK PORT
INPUT
REF
MONITOR
IRQ AND
STATUS
LOGIC
DIGITAL
INTERFACE
IRQ
SYSCLKN
SYSCLKP
CLKINN
CLKINP
M0 TO M7
REFA
REFAA
OUT0P
PHASE
CONTROLLER
DDS/DAC
AD9547
2 OR 4
OUT0N
OUT_RSET
OUT1P
OUT1N
POST
DIV
POST
DIV
CLOCK
DISTRIBUTION
REFB
REFBB
DIFFERENTIAL
OR
SINGLE-ENDED
EXTERNAL
ANALOG
FILTER
0830
0-
009
Figure 32. Detailed Block Diagram
OVERVIEW
The AD9547 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference but with
jitter characteristics primarily governed by the system clock. The
AD9547 supports up to four reference inputs and a wide range of
reference frequencies. The core of this product is a digital phase-
locked loop (DPLL). The DPLL has a programmable digital loop
filter that greatly reduces jitter transferred from the active
reference to the output. The AD9547 supports both manual and
automatic holdover modes. While in holdover mode, the AD9547
continues to provide an output as long as the DAC sample clock
is present. The holdover output frequency is a time average of
the output frequency history just prior to the transition to the
holdover condition.
The device offers manual and automatic reference switchover
capability if the active reference is degraded or fails completely.
A direct digital synthesizer (DDS) and integrated DAC constitute
a digitally controlled oscillator (DCO). The DCO output is
a sinusoidal signal (450 MHz maximum) at a frequency that is
determined by the active reference frequency and the programmed
values of the reference prescaler (R) and feedback divider (S).
Although not explicitly shown in Figure 32, the S divider has
both an integer and fractional component, which is similar to
a fractional-N synthesizer.
The SYSCLKx input provides the sample clock for the DAC, which
is either a directly applied high frequency source or a low frequency
source coupled with the integrated PLL-based frequency multiplier.
The low frequency option also allows for the use of a crystal
resonator connected directly across the SYSCLKx inputs.
The DAC output routes directly off chip where an external filter
removes the sampling artifacts before returning the signal on chip
at the CLKINx inputs. Once on chip, an integrated comparator
converts the filtered sinusoidal signal to a clock signal (square
wave) with very fast rise and fall times.
The clock distribution section provides two output drivers. Each
driver is programmable either as a single differential LVPECL/
LVDS output or as a dual single-ended CMOS output. Further-
more, a dedicated 30-bit programmable divider precedes each
driver. The clock distribution section operates at up to 725 MHz.
This enables use of a band-pass reconstruction filter (for example,
a SAW filter) to extract a Nyquist image from the DAC output
spectrum, thereby allowing output frequencies that exceed the
typical 450 MHz limit at the DAC output.
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| AD9547BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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