y = min(x0, x
參數(shù)資料
型號: AD9547BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 5/104頁
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9547 Mask Change 20/Oct/2010
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
AD9547
Data Sheet
Rev. E | Page 102 of 104
The min() function
y = min(x0, x1, ... xn)
where:
x0 through xn is a list of real numbers.
y is the number in the list that is the farthest tothe left on the
number line.
The max() function
y = max(x0, x1, ... xn)
where:
x0 through xn is a list of real numbers.
y is the number in the list that is the farthest to the right on the
number line.
The log2() function
log2(x) =
)
2
(
)
(
ln
x
ln
where: ln() is the natural log function.
x is a positive, nonzero number.
Assume that the coefficient calculations for α, β, γ, and δ above
yield the following results:
α = 0.012735446
β = 6.98672 × 105
γ = 7.50373 × 105
δ = 0.002015399
These values are floating point numbers that must be quantized
according to the bit widths of the linear and exponential com-
ponents of the coefficients as they appear in the register map.
Note that the calculations that follow indicate a positive value
for the register entries of β and γ. The reason is that β and γ,
which are supposed to be negative values, are stored in the
AD9547 registers as positive values. The AD9547 converts the
stored values to negative numbers within its signal processing
core. A detailed description of the register value computations
for α, β, γ, and δ follows.
Calculation ofthe α RegisterValues
The quantized α coefficient consists of four components: α0, α1,
α2, and α3, according to
α ≈ αquantized = α0 × 216 α1 2 + α3
where:
α0, α1, α2, and α3 are the register values.
α2 provides front-end gain.
α3 provides back-end gain.
α1 shifts the binary decimal point of α0 to the left to accommodate
small values of α.
Calculation of α1 is a two-step process, as follows:
w = if(α <1, ceil(log2(α)), 0)
α1 = if(α <1, min[63, max(0, w)], 0)
If gain is necessary (that is, α > 1), then it is beneficial to apply
most or all of it to the front-end gain (α2) implying that the cal-
culation of α2 is to be done before that of α3. Calculation of α2
is a three-step process that leads directly to the calculation of α3.
x = if(α > 1, ceil(log2(α)), 0)
y = if(α > 1, min[22, max(0, x)], 0)
α2 = if(y ≥ 8, 7, y)
α3 = if(y ≥ 8, y – 7, 0)
Calculation of α0 is a two-step process, as follows:
z = round(α × 216+ α1 α2 α3)
α0 = min[65535, max(1, z)
Using the example value of α = 0.012735446 yields
w = 6, so α1 = 6
x = 0 and y = 0, so α2 = 0 and α3 = 0
z = 53416.332099584, so α0 = 53416
This leads to the following quantized value, which is very close
to the desired value of 0.012735446:
αquantized = 53416 × 222 ≈ 0.01273566821
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