參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/104頁(yè)
文件大小： 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
Data Sheet
AD9547
Rev. E | Page 101 of 104
CALCULATING THE DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients (α, β, γ, and δ, as shown in
Figure 39) relate to the time constants (T1, T2, and T3) that are
associated with the equivalent analog circuit for a third-order loop
filter (see Figure 66). Note that AD9547 evaluation software
contains a profile designer that will compute these coefficients
for you.
R2
FROM
CHARGE
PUMP
TO
VCO
R3
C3
C1
C2
0
8300-
042
Figure 66. Third-Order Analog Loop Filter
The design process begins by deciding on two design parameters
related to the second-order loop filter shown in Figure 67: the
desired open-loop bandwidth (fP) and the phase margin (.
R2
FROM
CHARGE
PUMP
TO
VCO
C1
C2
0
8300-
043
Figure 67. Second-Order Analog Loop Filter
An analysis of the second-order loop filter leads to its primary
time constant, T1. It can be shown that T1 is expressible in terms
of fP and as
)
cos(
)
sin(
1
P
1
ω
T
where ωp = 2πfP
An analysis of the third-order loop filter leads to the definition
of another time constant, T3. It can be shown that T3 is expressible
in terms of the desired amount of additional attenuation intro-
duced by R3 and C3 at some specified frequency offset (fOFFSET)
from the PLL output frequency.
OFFSET
ATTEN
3
ω
T
1
10 10
where ωOFFSET = 2πfOFFSET
Note that ATTEN is the desired excess attenuation in decibels (dB).
Furthermore, ATTEN and ωOFFSET should be chosen so that
P
3
f
T
5
1
With an expression for T1 and T3, it is possible to define an adjusted
open-loop bandwidth (fC) that is slightly less than fP. It can be
shown that ωC (fC expressed as a radian frequency) is expressible
in terms of T1, T3, and θ (phase margin) as follows:
1
)
tan(
1
)
tan(
2
3
1
3
1
3
1
3
1
3
1
3
1
C
T
ω
It can also be shown that the adjusted open-loop bandwidth
leads to T2 (the secondary time constant of the second-order
loop filter), which is expressed as
3
1
C
2
T
ω
T
2
1
Calculation of the digital loop filter coefficients requires a
scaling constant, K (related to the system clock frequency, fS),
and the PLL feedback divide ratio, D.
S
f
K
33
2
125
,
578
,
517
,
30
1
V
U
S
D
where S, U, and V are the integer and fractional feedback divider
values that reside in the profile registers.
Keep in mind that the desired integer feedback divide ratio is one
more than the stored value of S (hence, the +1 term in the
equation for D in this equation). This leads to the digital filter
coefficients given by
2
2
1
2
C
3
C
1
C
1
2
C
T
ω
T
ω
T
ω
K
T
D
T
ω
α
2
1
S
T
f
β
1
32
1
ST
f
γ
32
3
ST
f
δ
32
Calculation of the coefficient register values requires the appli-
cation of some special functions, which are described as follows:
The if() function
y
= if (test_statement, true_value, false_value)
where:
test_statement
is a conditional expression (for example, x < 3).
true_value
is what y equals if the conditional expression is true.
false_value
is what y equals if the conditional expression is false.
The round() function
y
= round(x)
If x is an integer, then y = x. Otherwise, y is the nearest integer to x.
For example, round(2.1) = 2, round(2.5) = 3, and round(3.1) = 3.
The ceil() function
y
= ceil(x)
If x is an integer, then y = x. Otherwise, y is the next integer to
the right on the number line. For example, ceil(2.8) = 3,
whereas ceil(2.8) = 2.
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