參數(shù)資料
型號(hào): AD9547BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 96/104頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告: AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
Data Sheet
AD9547
Rev. E | Page 91 of 104
Table 126. IRQ Clearing for History Update, FrequencyLimit, and Phase Slew Limit
Address
Bit
Bit Name
Description
0x0A07
[7:5]
Unused
Unused.
4
History updated
Clears history updated IRQ.
3
Frequency unclamped
Clears frequency unclamped IRQ.
2
Frequency clamped
Clears frequency clampedIRQ.
1
Phase slew unlimited
Clears phase slew unlimitedIRQ.
0
Phase slew limited
Clears phase slew limitedIRQ.
Table 127. IRQ Clearing for Reference Inputs
Address
Bit
Bit Name
Description
0x0A08
7
Ref AA new profile
Clears Ref AA new profile IRQ.
6
Ref AA validated
Clears Ref AA validated IRQ.
5
Ref AA fault cleared
Clears Ref AA fault clearedIRQ.
4
Ref AA fault
Clears Ref AA fault IRQ.
3
Ref A new profile
Clears Ref A new profile IRQ.
2
Ref A validated
Clears Ref A validated IRQ.
1
Ref A fault cleared
Clears Ref A fault clearedIRQ.
0
Ref A fault
Clears Ref A fault IRQ.
0x0A09
7
Ref BB new profile
Clears Ref BB new profile IRQ.
6
Ref BB validated
Clears Ref BB validated IRQ.
5
Ref BB fault cleared
Clears Ref BB fault clearedIRQ.
4
Ref BB fault
Clears Ref BB fault IRQ.
3
Ref B new profile
Clears Ref B new profile IRQ.
2
Ref B validated
Clears Ref B validated IRQ.
1
Clears Ref B fault clearedIRQ.
0
Ref B fault
Clears Ref B fault IRQ.
0x0A0A
[7:0]
Unused
Unused.
0x0A0B
[7:0]
Table 128. Incremental Phase Offset Control
Address
Bit
Bit Name
Description
0x0A0C
[7:3]
Unused
Unused.
2
Reset phase offset
Resets the incremental phase offset to 0. This is an autoclearing bit.
1
Decrement phase
offset
Decrements the incremental phase offset by the amount specifiedin the incremental
phase lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
0
Increment phase
offset
Increments the incremental phase offset by the amount specifiedinthe incremental phase
lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
Table 129. Reference Profile Selection State MachineStartup1
Address
Bit
Bit Name
Description
0x0A0D
[7:4]
Unused
Unused.
3
Detect BB
Setting this bit starts the profile selectionstate machine for Input Reference BB.
2
Detect B
Setting this bit starts the profile selectionstate machine for Input Reference B.
1
Detect AA
Setting this bit starts the profile selectionstate machine for Input Reference AA.
0
Detect A
Setting this bit starts the profile selectionstate machine for Input Reference A.
1
All bits in this register are autoclearing.
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